MXPA01006994A - Dynamic damping clamper arrangement associated with s-shaping capacitor - Google Patents

Abstract

A resistor-capacitor-diode clamp is coupled to an S-capacitance of a horizontal deflection circuit output stage for reducing ringing by causing critical damping. The supply voltage of the output stage varies at a vertical rate parabolic manner for modulating the horizontal deflection current to provide East-West correction. A clamp capacitor of the clamp has a terminal that is direct current coupled to the supply voltage. Therefore, each terminal of the clamp capacitor has the same vertical rate parabola component. Consequently, the DC voltage difference developed between the terminals of the clamp capacitor does not include any vertical rate parabola component. The result is that the sensitivity of the damping to the supply voltage vertical rate variations is, advantageously, eliminated or reduced.

Description

ARRANGEMENT OF DYNAMIC CUSHIONING FIXER ASSOCIATED WITH A SHAPED CAPACITOR DESCRIPTION OF THE INVENTION The invention relates to a dynamic fixer arrangement of a deflection circuit. A television, computer or monitor receiver may have the ability to selectively present image information in the same color cathode ray tube (CRT) using a deflection current at different horizontal scanning frequencies. Typically, a capacitor S is coupled to a horizontal deflection winding of a horizontal deflection circuit output stage to correct a terrestrial beam error related to deflection referred to as correction S. A horizontal rate synchronization signal that controls The horizontal deflection circuit can be subjected to an abrupt phase change in a horizontal period that occurs during the vertical blanking interval. Such abrupt change of phase can be, for example, deliberately introduced to block the unauthorized video recording of the video signal. Consequently, the energy stored in an inductance coupled to the supply voltage of the physical horizontal deflection circuit output stage can be increased. The increased stored energy is subsequently dissipated. However, disadvantageously, the return to the steady-state operation may be accompanied by an oscillation in currents and voltages produced in the horizontal deflection circuit output output stage. A resistor-capacitor-diode (RCD) fastener coupled through the capacitance S has been used to reduce said oscillation by forcing the horizontal deflection circuit output stage to operate close to the critical damping. Another type of distortion that is corrected is called East-West distortion or cushion distortion. A known way to provide the correction of the East-West distortion is to vary the magnitude of the supply voltage of the horizontal deflection circuit output stage in a vertical-rate parabolic shape to modulate the horizontal deflection current. The magnitude of the supply voltage is controlled in a conventional manner, according to a vertical-rate parabola signal. In such an arrangement, the degree of damping provided by the aforementioned resistor-capacitor-diode clamp coupled through the capacitance S may, undesirably, vary as the supply voltage varies during the vertical scan. It may be desirable to reduce the sensitivity of the damping to vertical regime variations of the supply voltage. To carry out a feature of the invention, the terminal pair of the fixator capacitor of the RCD fastener is coupled between the supply voltage and the capacitance S. Each terminal of the fastener capacitor develops an equal amount of the parabola component of vertical regime. Consequently, the voltage difference developed between the terminals of the fixator capacitor does not include any parabola component of vertical regime. Therefore, the damping sensitivity of the vertical regime variations of the supply voltage, advantageously, is eliminated or reduced. A noodle display deflection apparatus, modalizing an aspect of the invention includes a source of an input signal at a frequency related to a horizontal deflection frequency. A horizontal deflection winding is coupled to a return capacitance and to a switch, responsive to the first input signal, to generate a horizontal deflection current in the horizontal deflection winding. An S-shaped capacitor is coupled to the horizontal deflection winding to develop a voltage in the S-shaped capacitor that varies in a way to provide horizontal linearity distortion correction. A source of a second signal that varies to a sequence related to a vertical deflection frequency is coupled to the S-shaped capacitor to vary the voltage of the S-shaped capacitor in accordance with it to provide the distortion correction of the S-shaped capacitor. West. A third capacitor is coupled to a rectifier to form a fixing circuit to set the voltage of the S-shaped capacitor, during a portion of a horizontal period. The third capacitor has a first terminal coupled to the S-shaped capacitor and a second terminal coupled to the second signal source to develop, from the second signal, voltage variations in each of the first and second terminals of the third Capacitor that compensate each other. The single figure illustrates a fixator, modeling an aspect of the invention, coupled through a switched capacitor S of a horizontal deflection circuit output stage. The single figure illustrates a horizontal deflection circuit output stage 101 of a television receiver having a multiple scanning frequency capability. Step 101 is energized through a regulated power supply 100 that generates a supply voltage B +. A conventional driver stage 103 is responsive to an input signal 107a at the selected horizontal scan frequency nfH. The driver stage 103 generates an excitation control signal 103a to control the switching operation in a switching transistor 104 of the output stage 101. By way of example, a value of n = 1 may represent the horizontal frequency of a signal television according to a given standard such as a broadcasting standard. The collector of transistor 104 is coupled to a terminal TOA of a primary winding T0W1 of a horizontal sweep transformer T0. The collector of transistor 104 is also coupled to a return capacitor 105. The collector of transistor 104 is further coupled to a horizontal deflection winding LY to form a resonant return circuit. The collector of transistor 104 is also coupled to a conventional fixative diode 108. Winding LY is coupled in series with a linearity inductor LIN and a non-switched tracker or capacitor S, CS1. The capacitor CS1 is coupled between a terminal 25 and a reference potential, or ground, GND, so that the terminal 25 is interposed between the inductor LIN and the capacitor S, CS1. The output stage 101 is capable of producing a deflection current iy. The current deflection i and substantially has the same predetermined amplitude for any selected horizontal scanning frequency of the selected signal 103a of a scale of 2fHa 2.4fH, and for a selected horizontal frequency of 1fH. The horizontal frequency of 1fH is, for example, approximately 16 KHz. The control of the amplitude of the deflection current iy is achieved by automatically raising the voltage B + when the horizontal frequency is increased, and vice versa, in order to maintain a constant amplitude of the deflection current iy. The B + voltage is controlled by a conventional regulated power supply 100 operating in a closed loop configuration through a feedback winding T0W2 of the transformer T0. The magnitude of the voltage B + is regulated, according to a rectified, horizontal feedback swept pulse signal, FB, having a magnitude that is indicative of the amplitude of current iy. A vertical-rate parabola signal E-W is generated in a conventional manner, not shown. The E-W signal is conventionally coupled to an energy supply 100 to produce a vertical-rate parabola component of voltage B + to provide the East-West distortion correction. A switching circuit 60 is used to correct a terrestrial beam error of light, such as linearity. The circuit 60 selectively couples none, only one or both a tracer capacitor CS2 and a tracer capacitor CS3 in parallel with the tracer capacitor CS1 non-switched. The selective coupling is determined as a function of the frequency scale from which the horizontal scanning frequency is selected. In the switching circuit 60, the capacitor CS2 is coupled between the terminal 25 and a drain electrode of a switch Q2 of the field effect transistor (FET). A source electrode of transistor Q2 is coupled to ground, GND. A protection resistor R2 which avoids excessive voltage through transistor Q2 is coupled through transistor Q2. A control signal 60a is generated in a digital to analog (D / A) converter 201. The control signal 60a is coupled through a voltage divider that includes a resistor R7 and a resistor R6 to a base electrode of a transistor of threshold determination Q3. An intermediate terminal 60c disposed between a resistor R3 and a resistor R5, forming an elevation voltage divider, is coupled to the collector of transistor Q3 and, through a resistor R4 to a gate electrode of transistor Q2. When the control signal 60a is large enough to turn on the transistor Q3, the gate voltage of the transistor Q2 is 0 and the transistor Q2 is turned off. On the other hand, when the control signal 60a is not large enough to turn on the transistor Q3, the gate voltage of the transistor Q2 is raised through the voltage produced by the resistors R3 and R5 and the transistor Q2 is turned on. The signal 60a is coupled through a threshold determination array of a Zener diode Z1 coupled in series with the resistor R6 'to develop a switching control signal 60b in a terminal 61b. The signal 60b is developed between the diode Z1 and the resistor R67 The signal 60b is coupled to the base of the transistor Q3 'via a base resistor R77 In the switching circuit 60, the capacitor CS3 is coupled between the terminal 25 and a drain electrode of a switch Q2 'of FET. The FET switch Q2 'is controlled via a control signal 60b in a manner similar to that which the FET switch Q2 is controlled by the control signal 60a. In this way, the resistors R3 \ R4 'and R5' and the transistor Q3 'are coupled together and perform similar functions as the resistors R3, R4 and R5 and the transistor Q3, respectively. When the frequency of the horizontal deflection current iy is 1fH, the signal 60a is at a minimum level of zero volts, so that the base voltage of the transistor Q3 does not exceed the advance voltage of the transistor Q3. Consequently, both transistors Q3 and Q3 'turn off and transistors Q2 and Q2' turn on. The result is that both capacitors S, CS2 and CS3, are capacitors S in circuit that are coupled in parallel with the capacitor S, CS1 not switched and establish a maximum value of capacitance S. When the frequency of the horizontal deflection current iy is equal to or greater than 2fH and less than 2.14fH, signal 60a is at an intermediate level of 5V, so that the base voltage of transistor Q3 exceeds the forward voltage of transistor Q3. However, the level of the signal 60a does not exceed the interruption voltage of the Zener diode Z1, consequently, the transistor Q3 is turned on, the transistor Q3 'is turned off, the transistor Q2 is turned off and the transistor Q2' is turned on. The result is that the capacitor S, CS2, is decoupled from the non-switched capacitor S, CS1, and the capacitor C, CS3 is coupled to the capacitor S, CS1, to establish an intermediate capacitance value S. When the horizontal deflection current frequency y is equal to or greater than 2.14fH, the signal 60a is at a maximum level of 10V, so that the base voltage of the transistor Q3 exceeds the advance voltage of the transistor Q3. Also, the level of the signal 60a exceeds the interruption voltage of the Zener diode Z1 by an amount sufficient to produce a base voltage of the transistor Q3 'which exceeds the forward voltage of the transistor Q3. Consequently, the transistors Q3 and Q3' are turned on and transistors Q2 and Q2 'are turned off. The result is that the capacitors S, CS2 and CS3, are decoupled from the non-switched capacitor S, CS1 and establish a minimum value of capacitance S.

A control circuit 61 includes a microprocessor 208 that is responsive to a data signal 209a generated in a data rate signal converter 209. The signal 209a has a numerical value that is indicative of the frequency of a synchronization signal, SYNCHRONIZATION HORIZONTAL, or deflection current iy. The converter 209 includes, for example, a counter that counts the number of clock pulses, during a given period of the HORIZONTAL SYNCHRONIZATION signal and generates a word signal 209a according to the number of clock pulses occurring in the period dice. The microprocessor 208 generates a control data signal 208a which is coupled to an input of the D / A converter 201. The value of the signal 208a is determined in accordance with the horizontal regime of the HORIZONTAL SYNCHRONIZATION signal. The D / A converter 201 generally, according to the data signal 208a, an analog control signal 60a in an individual terminal 61a. The signal 60a is at a level that is determined by the signal 208a, according to the frequency of the HORIZONTAL SYNCHRONIZATION signal. Alternatively, the value of the signal 208a can be determined by a signal 209b that is provided by a keyboard, not shown. A non-commutator setting circuit 300 includes a capacitor CD1 coupled in series with a parallel arrangement of a rectification diode DD1 and a setting resistor RD1. The locking circuit 300 is coupled between the terminal 25 of the capacitor CS1 and ground or through the capacitor S, CS1. The clamping circuit 300 is a circuit clamp at a horizontal scanning frequency of the signal 103a selected from the scale of 1fH to 2.4fH. The diode DD1 of the fixing circuit 300 rectifies peaks of the horizontal regime voltage component at the terminal 25 of the capacitor S, CS1. Rectification occurs mainly when the vertical scan is approximately one third above the display screen. The values of the R-C component of the fixing circuit 300 are selected to provide optimized damping, when the horizontal deflection current frequency iy is equal to or greater than 2fH. When the operating frequency is at a lower frequency, 1fH, the horizontal deflection supply voltage B + is reduced to 70V from a higher level near 140V. Therefore, the rectification provided by the diode DD1 of the fixing circuit 300 provides a lower voltage. The result is that the energy dissipated in resistor RD1 falls to approximately 25% of that of 2fH. Consistently and disadvantageously, at the lower frequency of 1fH, circuit 300 may not provide sufficient damping to prevent oscillation. Advantageously, a switched fixing circuit 303 is coupled to the terminal 25 and includes a capacitor CD2 coupled in series with a parallel arrangement of a rectifying diode DD2 and a damping resistor RD2. A terminal CD2a of the capacitor CD2 that is far from the terminal 25 is coupled to the supply voltage B + through a relay contact RB and a relay contact RA of a relay 302. The bore RL of the relay 302 is coupled between a supply voltage of 15V and the collector terminal of a relay control transistor Q4. The base terminal of transistor Q4 is coupled to terminal 61a. When the horizontal frequency is equal to or greater than 2fH, the signal 60a in the terminal 61a is at a higher level causing the bovine LR of the relay 302 to be energized through the transistor Q4. This results in decoupling of contact RA from contact RB. On the other hand, when the horizontal frequency is equal to 1fH, the signal 60a is at a lower level and causes the transistor Q4 to turn off in a way to couple the capacitor CD2 to the terminal where the voltage B + develops. In this way, the fixing circuit 303 and the tracking capacitor CS2 are elements in circuits when the selected horizontal scanning frequency is 1fH. The component values of the fixing circuit 303 are selected to supplement the damping provided by the circuit 300 providing the desired damping, when the frequency of the horizontal deflection current iy is equal to 1fH. Advantageously, both the clamping circuit 300 and the circuit 303 together provide the damping required to eliminate oscillation, when the horizontal deflection current frequency iy is equal to 1fH- Similarly to the capacitor CS2, the clamping circuit 303 has no effect on frequencies greater than 1fH.

If the capacitor CD2 of the fixing circuit 302 is coupled to ground as the capacitor CD 1, it could have differentiated the parabolic voltage component of the cushion correction E-W developed in the terminal 25 of the S-shaped capacitors in circuit. This is because the supply voltage B + which determines the voltage at terminal 25 varies in a parabolic form of vertical regime. Said differentiation could have resulted in an undesirable sawtooth current component that varies at a vertical rate in current iy of horizontal winding Ly. Disadvantageously, the undesirable saw current component could have caused the sides of the tracer to tilt. To carry out an aspect of the invention, in contrast to the clamping capacitor CD1, the terminal CD2a of the clamping capacitor CD2 which is remote from the terminal 25 is coupled, DC, to the supply voltage B + through the relay contacts RB and RA, instead of ground. Each terminal of the capacitor CD2 develops the same amplitude and phase of the vertical-rate parabola component of the B + voltage. Consequently, the voltage difference developed between the terminals of the clamping capacitor CD2 excludes any difference in vertical-rated parabola voltage. In this way, the rectified spikes of the voltage on the capacitor S, CS2, for example, and the supply voltage modulation B + are approximately equal in magnitude. Therefore, the vertical regime variations in the supply voltage B +, advantageously, have no effect on the damping function.

The degree of damping required is greater when the frequency of the horizontal deflection current iy is equal to 1fH, than when the frequency of the horizontal deflection current is greater. Therefore, the coupling of capacitor CD1 to voltage B + is not as important as in the case of capacitor CD2.

Claims (6)

1. - A video presentation deflection apparatus, comprising: a source of an input signal at a frequency related to a horizontal deflection frequency; a horizontal deflection winding coupled to a return capacitance and to a switch, responsive to the first input signal, to generate a horizontal deflection signal in the horizontal deflection winding; an S-shaped capacitor coupled to the horizontal deflection winding to develop a voltage in the S-shaped capacitor that varies in a way to provide horizontal linearity distortion correction; a source of a second signal varying at a frequency related to a vertical deflection frequency coupled to the S-shaped capacitor to vary the voltage of the S-shaped capacitor in accordance therewith to provide the East-West distortion correction; and a third capacitor coupled to a rectifier to form a fixator circuit to set the voltage of the S-shaped capacitor, during a portion of a horizontal period, said third capacitor having a first terminal coupled to the S-shaped capacitor and a second terminal coupled to the second signal source to develop, from the second signal, voltage variations in each of the first and second terminals of the third capacitor that compensate each other.

2. A video presentation deflection apparatus according to claim 1, further comprising a source of a supply voltage sensitive to a second signal and coupled to the switch through a supply inductance to modulate the deflection current to provide the East-West distortion correction according to a voltage variation of said supply voltage, the supply voltage producing on the first and second terminals of the third capacitor the compensation voltage variations, respectively.

3. A video presentation deflection apparatus according to claim 2, wherein the second terminal is coupled to the supply voltage source through a path that excludes the first terminal.

4. A video presentation deflection apparatus according to claim 1, wherein the fixing circuit sets the voltage of the S-shaped capacitor, mainly during the horizontal cycles that occur at the beginning of a vertical tracking interval.

5. A video presentation deflection apparatus according to claim 1, further comprising a second switch for coupling the third capacitor to the S-shaped capacitor, when the horizontal frequency enters a first level and for decoupling the third capacitor of the S-shaped capacitor, when the horizontal frequency is at a second value.

6. A video presentation deflection apparatus according to claim 1, wherein the third capacitor is coupled to a resistor that is coupled in parallel with the rectifier.