CHIP SEMICONDUCTOR WITH SURFACE COATING FIELD OF THE INVENTION The invention relates to a semiconductor chip made with at least one layer of a semiconductor substrate, at least fewer connections or associated circuits in a group and with an electrically conductive protection layer associated through it. at least one of those groups of circuits and electrically connected to one of the circuits. BACKGROUND OF THE INVENTION A semiconductor chip of this type is known from EP 0 378 306 7A2. In that semiconductor chip is associated a first group of circuits in a security zone and a second group of circuits in an unsecured zone. The securing of the first zone is carried out in known semiconductor chips by means of a conductive layer which is associated to the first group of circuits through the interconnection plane of the first group of circuits. That conductive layer is electrically connected to the group of circuits, where the ordered function of that group of connections occurs only in the case of an intact layer. The first group of circuits here includes a microprocessor as well as its peripheral circuits such as memory and transfer logic. In the memoirs, secret information can be kept secret. It can also be thought that the microprocessor has a special structure, which is especially suitable for relevant safety functions. It can also be thought that the microprocessor has a special structure that is especially suitable for relevant safety functions. By means of the conductive layer, it is constantly verified that it is intact, by avoiding an inspection by means of an electronic scanning microscope during the operation of the circuit. However, it is possible, as before, to remove the protective layer and place spare parts, which are not in critical safety zones. In this way an inspection of the circuits in operation can be carried out, although only under currently very expensive conditions. Also EP 0 169 941 A1 shows a. semiconductor circuit with a paging layer, which protects the parts of the circuit that are below it in the form of an equipotential surface. The passivation layer is considered as an active conductive path in a safety logic circuit, in such a way that its elimination interrupts the function of the chip and makes dynamic analysis impossible. When it is possible instead of the passivation layer to place a type of bypass bypass circuit, which certainly does not comply with the function of conduction of the passivation layer but the shielding or protection function in this known protection circuit of the semiconductor circuit , it is activated again. EP 0 300 864 A2 shows the provision of a conductive protective layer consisting of two partial layers whose capacity is evaluated. The substitution of one or both partial layers by other conductive structures is not possible directly, but the formation of the capacity by means of other structures that leave at least parts of the circuit that evade the security points. In any case, the separation of the layers and subsequent placement can not be determined later to carry out a subsequent exploration of the semiconductor chip. One method to remove the layers and also to apply new layers such as bypass circuits is the focussed-ion-beam (FIB) method. This was developed mainly for the elimination of errors and the restructuring, but represents a considerable danger to the critical semiconductor chip for security. SUMMARY OF THE INVENTION It is therefore the task of the invention to present a semiconductor circuit that is safe against attacks by the FIB. The task is solved according to claim 1 because the substrate of a semiconductor chip at least has a protection sensor that is shaped in such a way that it can store a state in non-volatile form, and because the protection sensor with its detection connection is connected to the conductive protection layer or at least one of the conductive protection layers and the output connection of the protection sensor is connected to one of the circuits in such a way that a certain function is not possible when a defined non-volatile level is found at the output of the protection sensor. A protection sensor can advantageously be a transistor with very thin gate oxide in comparison with the transistors of the circuits. But other parts that serve as safety devices ("fuses") like diodes can also be used. It is essential for a constructive part that is sensor of protection of the function, which can be modifier in a non-volatile way by means of a voltage. In this respect, non-volatile means that a stored state not only remains after the deactivation and reapplication of the supply voltage, but a withdrawal and re-application of a conductive layer forming a connection is detected and maintained. It can also be determined in the case of an intact layer if it was previously separated or if at least the attempt was made. It has been shown that the structures treated with the FIB method are electrically charged. The voltage thus formed is detected by the protection sensors and evaluated by means of some parts of the circuit (s). When a transistor protection sensor is a very thin gate oxide in comparison with the transistors of the circuits this voltage is disturbed by the ion radiation. This can be evaluated in a simple way. The protection sensors can on the one hand be distributed covering the surface of the semiconductor chip on the other hand a small number of sensors is sufficient. A special advantage of the invention is a protection sensor configured as a non-volatile memory cell which is formed with drain and source diffusion zones formed on both sides of the channel zone in the semiconductor substrate as well as a gate electrode positioned by at least partially above the channel zone and two control gate electrodes positioned above insulated gate electrodes, wherein one control gate electrode forms the detection connection and the other control gate electrode as well as the control gate electrode. diffusion zone are linked with an evaluator circuit. This new type of non-volatile memory cell leads to a voltage caused by ion radiation to a change in the load in the isolated gates, which can not flow. Through the second connection to the control gate as well as the connections in the diffusion zones it can be read and thus the modified state of the memory cell detected at any time. Advantageously, the insulated gate is pre-charged, for which several previous loads with different polarities are applied to the protection sensors, which leads to a more secure detection of a manipulation. BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described in detail below with an example of embodiment with the help of the figures. Shown in Figure 1: a possible embodiment of a protection layer Figure 2: The image of the main circuit of an evaluation circuit with a protection sensor according to the invention; Figure 3: a top view of a protection sensor according to the invention in a conformation in the form of a non-volatile memory cell; and Figure 4: the main representation of an evaluator circuit in connection with a non-volatile memory cell. . DESCRIPTION OF THE INVENTION Figure 1 shows a protective coating in the form of a conduit extending in the shape of a meander with two connection points A, B which is preferably made for semiconductor circuits in the uppermost metal layer of a process of conventional production. The connection points A, B make contact with the circuit plane. There they can be connected to a circuit, as shown in FIG. 2. A generator of signal GENs in the emitter device 1 on the semiconductor chip, produces a signal that in the example shown is sent through the amplifiers Vl, V2 of a protective conduit SL, as shown in figure 1, and a reference conduit RL. The connection point B of the protective conduit is connected to the gate contacts of two transistors TI, T2 connected in the form of a CMOS inverter with a thin gate oxide layer, which serve as an SS protection sensor. The output of the protection sensor SS is also connected to the second connector of the reference circuit RL with the inputs of a KOM comparator, whose output signal shows whether the protection sensor SS is intact or not. The protection sensor SS and the comparator KOM thus form a receiver circuit 2. When the protection sensor SS is intact, its output sends the same signal as the reference line L. If the protection sensor is disturbed, however, due to a high voltage as a consequence of the attack by ion radiation, its output constantly gives either a logical one or a logical zero, which is recognized by the KOM comparator. The output signal of the comparator KOM, produces that the circuit made in the semiconductor chip can not fulfill its determined function. Figure 3 shows a top view of a representation mainly of a non-volatile memory cell according to the invention with two control gate electrodes. Between the two diffusion zones 10, 11, which act as a drain and source of a field effect transistor, a channel area not described in detail is formed, which is covered by a partial area of an isolated gate electrode 12, with a gate called floating. The insulated layer between the channel zone and the source or drainage area 11 on the one hand and the insulated gate electrode 12 on the other hand is a small area especially thin and forms there a tunnel window 13. Through a first area of the isolated gate electrode 12 is a first control gate electrode 14 and is placed on a second zone of a second control gate electrode 15. The diffusion zone 10, 11 and the control gate electrodes 14, 15 present connections A, A ', B, B' or C. The novel memory cell can advantageously be used instead of the transistors with the thin gate oxide according to Figure 2. Here then the connection C of the memory cell must be connected to connection B of the protective conduit SL. The connection B of the memory cell and the connections of the diffusion areas A, A 'of the memory cell are used on the one hand for the application of a preload to the isolated gate electrodes and on the gold side to evaluate the Load state of the isolated gate electrode are connected to an AWS evaluator circuit. This is shown in Figure 4. Preloading is performed in an advantageous embodiment of the invention prior to sending the semiconductor chip during the test phase is applied to the isolated gate electrodes by means of the application of a high voltage programming for example 16V between one of the conduits B or B 'of the first control gate electrode 14 and the connection A of the diffusion zone 11 on the insulated gate electrode. By means of this load a determined initial tension is formed in the memory transistor. The initial voltage is therefore the measurement of the load on the insulated gate electrode. If an IBF attack occurs, then a voltage is formed between the second signal gate electrode 15 and the channel zone. This voltage leads to a tunnel current through the tunnel window 13 and thus to a modification of the load on the gate electrode 12. This change in the load can be detected by means of the application of a variable reading voltage. in the first control electrode 14 by means of the AWS evaluation circuit. A modified initial voltage means that the charge on the insulated gate electrode was modified. If a non-volatile FIB attack was not retained in this way, they can be activated in the next operation of the semiconductor chip, suitable defense mechanisms. In the isolated gate electrodes 12 both positive and negative charges and with different protection sensors can be applied as preloads, also loads of different values and polarities to increase the security of the detection of a FIB attack. The special advantage of the use according to the invention of a protective layer in conjunction with a protection sensor is that the protection sensor is subjected to an ion-radiation examination of the protective layer in a non-volatile manner and with this also a subsequent repair of the protective layer or the corresponding deflection conduits can not lead to a certain function of the semiconductor chip.