MXPA01001298A - Cached chainback ram for serial viterbi decoder - Google Patents

Abstract

A serial Viterbi decoder having a chainback cache is provided for use in a mobile telephone. In one embodiment described herein, the decoder includes a branch error metric block, an add-compare-select unit, and a chainback block including a chainback RAM, a full chainback cache and chainback controller circuitry. The chainbackcache caches decision bits from previous process cycles such that full chainback operations need not always be performed. The chainback cache is configured to cache on all reads. With the chainback cache, significant savings in power consumption and processing time may be achieved with only a relatively modest increase in the amount of circuitry required. In another embodiment, a full chainback cache is not provided. Rather, the chainback block instead includes an L+1 bit RAM, an updown counter and a shift register configured to emulate a chainback cache. In still another embodiment, an L bit shift register is employed instead of the combination of the L+1 bit RAM and updown counter. In the various embodiments, the chainback block may be configured to perform only one chainback read in each process cycle or may be configured to perform m chainback reads in each process cycle. In still other embodiments, the chainback block is configured to perform chainback operations based on a through b reads where the cache is accessed for each read after a reads have been done until b reads have been performed or a match is obtained. In still further embodiments, the chainback block is configured to perform chainback operations over multiple process cycles rather than only a single process cycle.

Description

RANDOM ACCUMULATION ACCESS REPORT IN CHAIN WITH ANTIEMMERY FOR VITERBI DECODER IN SERIES BACKGROUND OF THE INVENTION I. FIELD OF THE INVENTION The invention relates generally to Viterbi decoders in series and in particular to Viterbi decoders in series for use within multiple code wireless access (CDMA) wireless communication systems.

II. Description of the Related Art Figure 1 is a block diagram illustrative of a variable speed CDMA transmission system 10 described in the interim standard of the Industry Association of Telecommunications TIA / EIA / IS-95-A Mobile Station - Base Station Compatibility Standard for Dual-Mode ideband Spread Spectrum Cellular System. This transmission system may be provided, for example, within a base station of a cellular transmission system for use in the transmission of signals to mobile telephones within a cell surrounding the base station. An input line 11 provides a voice or data signal that can be analog or digital. In the following example, it will be assumed that the input signal is a voice signal. The input line can be a digital or analog line of the telephone, switched, public (PSTN) or other voice signal source. If the input speech signal is analog, the signal is sampled and digitized by an analog-to-digital converter (not shown). A variable rate data source 12 receives the digitized samples of the speech signal and to provide packets of equal frame lengths. The variable rate data source 12 can convert, for example, the digitized samples of the input voice to speech parameters, digitized, representative of the input speech signal using predictive, linear (LPC) coding techniques. In one embodiment, the variable rate data source is a variable speed vocoder as described in detail in U.S. Patent Number 5,414,796. The variable rate data source 12 provides variable speed data packets at four possible frame rates of 9600 bps, 4800 bps, 2400 bps and 1200 bps, referred to herein as full, half, quarter and full speeds. an eighth The full-rate encoded packets contain 172 bits of information, the samples coded at half speed contain 80 bits of information, the samples coded at a quarter speed contain 40 bits of information and the samples coded at one eighth of speed contain 16 bits of information. information. The packets despite the size are all of one length of one frame in duration, that is, 20 ms. Other systems may employ other data rates or packet sizes. In the present, the terms "box" and "pack" can be used interchangeably. The packets are encoded and transmitted at different speeds to compress the data contained in them, in part, in the complexity or quantity of information represented by the table. For example, if the input speech signal includes little or no variation, perhaps because the speaker is not speaking, the information bits of the corresponding packet can be compressed and encoded at one-eighth speed. This compression results in a loss of resolution of the corresponding portion of the speech signal, but, since the corresponding portion of the speech signal contains little or no information, the reduction in signal resolution will typically not be noticeable. Alternatively, if the corresponding input speech signal of the packet includes a lot of information, perhaps because the loudspeaker is actively vocalizing, the packet is coded at full speed and the information bits of the packet are not compressed completely.

This compression and coding technique is used to limit, on average, the amount of signals that are transmitted at any time to allow the complete bandwidth of the transmission system to be used more effectively to allow, for example, that a greater number of telephone calls be processed at any time. The variable speed packets generated by the data source 12 are provided to the packetizer 13 which selectively append cyclic redundancy check (CRC) bits and queue bits. The variable rate packets from the packetizer 13 are then provided to the encoder 14 encoding the bits of the variable speed packets for error detection and correction purposes In one embodiment, the encoder 14 is a serial Viterbi encoder. convolutional velocity 1/3 convolutionally coded symbols are then provided to a modulator 16 that generates a modulated signal In U.S. Patent Nos. 5,103,459 and 4,901,307 an implementation of a CDMA modulator is described in detail. then the digital-to-analog converter 22 is provided for conversion to an analog signal, then the transmitter 24 is provided which upconverts and amplifies the signal for transmission through the antenna 26. Figure 2 illustrates the relevant components of a mobile phone 28 or another mobile station that receives the transmitted signal. received by the antenna 30, it is downconverted and amplified, if necessary, by the receiver 31 and demodulated by a demodulator 32 in a stream of symbols that remain convolutionally encoded. The signal is then provided to a serial Viterbi decoder 34 that decodes a convolutionally encoded symbol stream. The decoder also subdivides the received signal into packets and determines the corresponding frame rate for each packet. The frame rate can be determined, for example, by detecting the duration of the individual bits of the frame. In copending U.S. Patent Application Serial No. 08 / 126,477 filed September 24, 1993, and assigned to the assignee of the present invention and incorporated herein by reference, aspects of an exemplary Viterbi decoder are described. . To decode the symbol stream, the decoder 34 employs a branch error metric block 36 that receives demodulator symbols and an addition comparison selection block (ACS) 38 that produces decision bits based on the symbols. To improve performance, the decoder is chained back from what it considers the best-state metric using a chain-backing block 40 that processes the decision bits received from ACS 38. In each process cycle, 2K_1 bits of data are stored. decision by the chain-backing block in a chain-backed RAM 41 where K is the restriction length of the code used by the encoder. The state with the best lowest state metric is passed from the ACS to the chain backing block as the best state. Once the process cycles have elapsed, the chain backup begins. The chain backup operation is controlled by a chain backup controller 42. The chain backup process is performed when reading from the chain-backed RAM the decision bit for the best state for the previous process cycle (L-1). The read decision bit is changed to the least significant bit of the best state. The chain backup block then reads from the chain-backed RAM the decision bit corresponding to the new value of the best state for the process cycle L-2. This process is performed a total of L times that finally read the decision bit of the best calculated state for process cycle 0. The final decision bit is the decoded information bit. Each bit that is read modifies the direction of the subsequent reading. In the next process cycle, L + l, the complete procedure is repeated again, reading the decision-state bits of the process cycles L down to 1. This continues for many process cycles as necessary to recover the required number of information bits for the particular system. F_n Figure 3 illustrates specific examples of chain-back operations. If the first chain backup occurs after 4 processing cycles and the best state is 101 after 4 processing cycles, then the readings taken to determine the chain backup process are those shown by the shaded entries in gray. The first state 101 of process cycle 3 will be read, then state 011 of process cycle 2, then state 111 of process cycle 1, then state 110 of process cycle 0, resulting in a decision bit of output of 0. At the beginning of process cycle 5, if the best state is 010, then the first reading results in the best state that fits 101. Therefore, the next three readings will follow the same route as before, specifically the shaded entry routes in gray. This time even if the output decision bit is read from process cycle 1, d enter resulting in a decision bit of 0. At the start of process cycle 6, if the best state is 001, then the first reading results in the best state that is set to 010. Therefore, the next three readings they will follow the same route again as before. This time enters, although the output decision bit is read out of the process cycle 2, thereby resulting in a decision bit of 1. With reference again to Figure 2, finally, the decoder 34 provides a decoded packet. together with a signal that identifies the detected frame rate for the packet. Both are transmitted to a frame quality check unit 43 which attempts to verify that transmission errors or frame rate detection errors have not occurred. In the exemplary mode, the frame quality check unit 43 performs a CRC, a symbol error rate check and a Yamamoto metric check. To perform the symbol error rate check, the frame quality check unit 43 pre-codes the symbols found in the decoded packet and compares them with the re-encoded symbols with the symbols input to the quality check unit of frame to detect any difference. To perform the Yamamoto metric verification, the frame quality check unit 43 applies the received frames to a grid route decoder and determines whether a resulting metric is acceptable. Acceptable frames are routed to a speech decoder 44 for conversion back to the digitized voice signals. The digitized speech signals are converted to analog signals by a digital-to-analog converter (not 'shown') for the final transfer through a speaker 46 of the mobile telephone such that a telephone operator can hear the voice signal that has been received. originally introduced to the complete system along line 11 of Figure 1. Although not shown, the mobile telephone of Figure 2 may have additional components for introducing a voice signal -analogical from the mobile telephone operator and for transmit and process the signal using CDMA techniques. The additional components of the mobile telephone may be similar to the components shown in Figure 1. Furthermore, although not shown, the transmission system of Figure 1 may have additional components provided to receive the signal transmitted from the mobile telephone to process and Transfer the signal as an analog or digital voice signal, perhaps on a PSTN • line. The additional conponents of the system of Figure 1 may be similar to the components shown in Figure 2. In this way, an important component of the complete system is the serial Viterbi decoder provided to decode the transmitted symbols. As noted, the decoder 34 makes use of a chain-back operation to improve performance. To gain a significant improvement in performance, the length of the chain backrest is preferably at least 3 to 5 times the encoder's restriction length (K = 9 for CDMA) with better performance with greater depth of chain backing . However, the longer the length of the chain backup, the greater the amount of the circuit area and the power required to implement the chain backup. A large circuit area is required since a large memory is required to store the backup decision bits in a chain. For example, for a restriction encoder K, 2K ~ 1 decision bits are stored for each bit of information. With a depth of chain backup of L, you need to store L * 2K ~ 1 bit. Because more power is required in order to generate a data directory, the chain-backing block needs to perform L readings. As well, there is a longer delay before the chain backup operation is completed. Although described with respect to a CDMA system employing a Viterbi decoder in series, similar problems can occur in most systems employing serial Viterbi decoders and also in the related decoder systems. Therefore, it would be desirable to provide a technique to substantially reduce the use of power and the processing time of the chain-backing block as long as it only requires a small increase in air and it is for that purpose that the aspects of the present invention.

SUMMARY OF THE INVENTION In accordance with one aspect of the invention, an improvement is provided within a Viterbi serial decoder to decode a convolutionally encoded stream of symbols using a chain backup memory that stores a plurality of decision bits for each of a plurality of process cycles. The improvement comprises a chain-backed cache, connected to the chain back-up memory, to store a sequence of decision bits determined by a previous process cycle. In an example mode, the serial Viterbi decoder includes a branch error metric block, an ACS, and a respired chain-link block that includes a chain-backed RAM, a complete chain-backed cache, and circuitry of chain backup driver. The chain backup cache is configured to store all readings in memory. In another example mode, a full cache-backed cache is not provided. Rather, the chain backup block includes a RAM of L + 1 bits, an up-down counter and a change register configured to emulate a chain-backed cache. In still another example mode, a change register of L bits is used instead of the combination of the RAM of L + l bits and the ascending-descending counter. In the various modalities, the chain-backing block can be configured to perform only one chain-back read in each process cycle and can be configured to perform chain-backed readings in each process cycle before attempting to use the cache . In still other modalities, the chain backup block is configured to perform a to b readings during each chain backup operation, where after readings, the cache is checked for each subsequent reading until readings have been made. or until a correspondence is obtained. In still further embodiments, the chain-backing block is configured to perform chain-back operations over multiple process cycles instead of just one individual process cycle. Combinations of characteristics of these modalities may also be appropriate. In the various exemplary implementations, by providing circuitry for caching the decision bits of the previous process cycles, significant savings in power consumption and processing time are typically achieved, with only a relatively modest increase in power consumption. amount of circuitry required. Methods of method and apparatus of the invention are described.

BRIEF DESCRIPTION OF THE DRAWINGS The characteristics, objects and advantages of the present invention will become more evident from the detailed description set forth below when taken in conjunction with the drawings in which characters of similar references are identified correspondingly to everything and where: Figure 1 is a block diagram illustrating relevant components of a variable speed CDMA transmission system; Figure 2 is a block diagram illustrating the relevant components of a mobile telephone or other mobile station that receives the signal transmitted by the CDMA transmission system of Figure 1 that decodes the signal using a Viterbi decoder in series with a block chain backup; Figure 3 is a diagram illustrating a chain backup operation performed by a chain back-up block of the mobile telephone of Figure 2; Figure 4 is a block diagram illustrating, at a high level, the relevant components of a mobile telephone or other mobile station configured in accordance with an exemplary embodiment of the invention, wherein a serial Viterbi decoder is provided which has a chain backing block with chain back cache; Figures 5A and 5B illustrate in detail a first embodiment of a chain backing block of the mobile telephone of Figure 4; Figures 6A and 6B illustrate in detail a second embodiment of a chain backing block of the mobile telephone of Figure 4; and Figure 7 illustrates in detail the relevant portions of a third mode of a chain back-up block of the mobile telephone of Figure 4.

DETAILED DESCRIPTION OF THE PREFERRED MODALITIES With reference to the remaining Figures, preferred and exemplary embodiments of the invention will now be described. Figure 4 illustrates the relevant components of a mobile telephone 128 or another mobile station that receives a transmitted signal from CDMA. The portions of the mobile telephone 128 operate in the same manner as the mobile telephone of Figure 2 and will only be briefly described. The CDMA signal is received by the antenna 130, downconverted and amplified, if necessary, by the receiver 131 and demodulated by a demodulator 132 in a stream of convolutionally decoded symbols. The convolutionally encoded symbols are then provided to a modified, serial Viterbi decoder 134 which decodes the symbol stream using a branch error metric block 136, an ACS 138, a back-up block 140. The chain backup block includes a chain-backed RAM 141, a chain-backed controller 142, and a chain-backed cache 145 configured to cache only the readings. The state with the lowest best-status metric is passed from the ACS to the chain-backing block as the best state where it is stored in the chain-backed RAM and is also stored in the chain-backed cache so that it is You can easily access again. As will be described later, the decoder does not really need to include a separate complete cache as shown in Figure 4. However, for reasons of clarity in describing the complete operation of the cached chain back-up system, it is first assumed that a complete cache is used. With the cached chain back-up system of Figure 4, the chain-back operation is performed when reading from the chain-backed cache 145, the decision bit representative of the best-status metric if the current metric of best Calculated state after a reading in the new process cycle corresponds to the best-condition start metric of the last process cycle. If the newly calculated metric of better status does not correspond, then the conventional chain backup is performed. More specifically, at the beginning of the process cycle, a signal is sent on this to the best-condition metric. A first decision bit is read from the daisy chain RAM from the location specified by encstate, and the read bit is changed to the least significant bit of encstate. The new value of in cs ta te is then compared against a value called the s t_beststa te that retains the best state metric for the previous process cycle. If the values correspond, it is necessary to perform additional readings to complete the backup and chain operation. In contrast, the final folder can be read simply from the cache. (The signals st stbes are not shown specifically in Figure 4 but are shown in other Figures described later). Assuming that the additional readings are to be performed, the chain backup block then reads from the daisy chain RAM the decision bit corresponding to the value in question for the decision bits described during the process cycle L -2. This process is performed at a total of L times by finally reading the decision bit of cs ta te calculated for process cycle 0. The final decision bit is the bit of decoded information. Each bit that is read modifies the direction of the subsequent reading. In the next process cycle L + l, the process is repeated again, reading the status decision bits of the process cycles L down to 1. This continues for many process cycles as necessary to recover the required number of process cycles. bits of information for the particular system. Once the conventional chain backup operation is finished, the entire sequence of decision bits generated by the conventional chain-back operation is stored in the chain-backed cache 145, such that, in the next process cycle, the complete chain-back operation does not have to be repeated. . More specifically, after a first cycle of the chain backup process has been completed, in the subsequent process cycles, the first reading will assume that the value it has at the beginning of the previous process cycle assumes. and the value of encstate therefore corresponds to the value of the s t_bes ts ta te. This is not always the case, since it is true that most of the time due to the convergence properties of the path of the convolutional codes. Therefore, in a given process cycle, it is likely that L-l readings will be the same as the previous process cycle and the final decision bit will be the second to last bit read during the previous process cycle. Therefore, the provision of the chain-backed cache allows the decision bits for the readings including the final decision bit to be read only from the cache, instead of being recalculated, thereby improving the performance Finally, the decoder 134 provides a decoded packet together with a signal identifying a frame rate detected for the packet, a frame quality check unit 143 that attempts to verify that there are no transmission errors or speed detection errors. occurrence using a CRC, a symbol error rate check and a Yamamoto metric check. Acceptable frames are routed to a voice decoder 144 for conversion back to digitized voice signals. The digitized speech signals are converted to analog signals by a digital-to-analog converter (not shown) for the final transfer through a loudspeaker 146 of the mobile telephone. Although not shown, the mobile telephone of Figure 4 may have additional conferers to introduce an analog voice signal from the mobile telephone operator and to process and transmit the signal using CDMA techniques. The additional components of the mobile telephone may be similar to the components shown in Figure 1. In this way, Figure 4 illustrates, at a high level, a mobile telephone employing a Viterbi serial decoder having a back-up block in chain with a complete cache, separated from chain backup configured to cache the readings. The logical cache circuit operates inherently to keep a copy of the various decision bits read in its own memory. Complete energy savings are achieved in that the power requirements of the cache are not greater than the energy reduction gained by not having access to memory backup RAM so frequently. Also, the total decoding time can be reduced, depending on the implementation, with respect to implementations without a chain-backed cache. Savings in decoding time can be achieved as a result of the system performing only a cache reading when a correspondence is presented, instead of performing additional readings of the back-up RAM in case of no correspondence. The reduction in decoding time is particularly significant in systems where the chain backup RAM is slower and the cache is faster. An example comparison between a performance of a backing block in non-cacheed chains and a cached chain backing block is as follows. For a channel 1 with an IS95 speed setting that has a frame error rate of 1%, a serial Viterbi decoder without cache can perform 289 memory backup operations with L = 63. It is noted that the last 72 bits of a packet are obtained through an individual memory backup operation. The total number of readings of the memory backup RAM is therefore 289 * 63 = 18207. Of the 100 data tables, in cs ta t e after a reading corresponds to the bests of the previous process cycle, an average of approximately 233 times per frame (of the 289 memory backup operations). In this way, the total number of memory backup RAM readings required using the cached chain back-up block is only 56 * 63 + 233 = 3761 thus representing average savings per frame of 14,446 readings. For an IS95A speed adjustment channel 2 having a frame error rate of 1%, a serial Viterbi decoder without cache could perform 437 memory backup operations with L = 95. It is noted that the last 104 bits of a packet are obtained through an individual chain-back operation. In this way, the total number of backup RAM readings in chain is therefore 437 * 95 = 41515. Of the. 23 data tables, after a reading corresponds to the beststa of the previous process cycle at an average of approximately 338 times per frame (of the 437 chain backup operations). In this way, the total number of back-up RAM readings required using the cached chain back-up block is only 99 * 95 + 388 = 9743, thus representing average savings per frame of 31,772 readings. Actual results may differ depending on the particular system. The chain backup block of Figure 4 can be implemented using any of a variety of other specific configurations also configured to provide an additional reduction in power usage or a reduction in the circuit area or both. Some specific example configurations will now be described with reference to the remaining Figures. Figures 5A and 5B illustrate a more efficient implementation of the chain-backing block that can further reduce the excess read to the chain-back RAM by employing a small RAM of L + 1 bits or a log file to store the bits of decisions read from each process cycle. The chain back-up block includes a back-up RAM 202, a RAM 204 of L + 1 bits, an up-down counter 206 and an interconnected change register 208 together with several registers and logical composites as shown. After L process cycles, the first chain backup operation begins. The best state for the previous process cycle. { bes ts ta t) is stored in the change register 208, the output of which is the value referred to above, in cs ta te. The read bits of the backup chain RAM 202 are stored in a RAM 204 of L + l bits (with an additional bit stored to make the circuitry simpler than if only L bits will be stored). A separate register 210 is used to keep track of the previous bests value that is referred to above as the s t_bes tsta. In the next process cycle, the new bests value is enclosed in the change register 208. The first reading of a process cycle results in a decision bit that is changed to the lowest bit of the change register 208. This bit is also stored in RAM 204 of L + l bits as before. If encstate now corresponds to the s t_bes ts ta e, then the bit of the smallest / oldest process cycle is removed from the RAM 204 of. L + l bits, thus becoming the output bit. This bit is the same bit that would have to result from which a complete chain backup operation has been performed in the chain backup RAM, it is obtained simply with less processing time and effort. If, after a reading, encstate does not correspond to the t_bes, the complete chain-back operation is performed, by simultaneously filling in L-1 locations of the RAM 204 of L + l bits. In any case, at the end of the process cycle, the previous value of beststa is stored in the process and the subsequent process cycles continue in the same way as the process cycle described above. When configuring the chain backup block with the RAM of L + l bits, less read operations are required by the chain backup RAM, whereby the use of full decoder power is further reduced. The implementation of Figures 5A and 5B may seem somewhat complex, but in comparison to an implementation that has a chain-backing block with an access cache accessed in each process cycle, the chain-backing blocks in Figures 5A and 5B only they require the addition of the up-down counter 206, the RAM 204 of L + l bits (or other log file) and the various individual bit registers and combination logic circuit as shown. This has the advantage that in the process cycles with a correspondence, it is only necessary to perform a reading of the backup RAM in chain instead of L, as well as a reading of the RAM of L + 1 bit and the writing that is relatively insignificant . In the non-matches of the process cycle, it is necessary to make L readings of the backup RAM in chain as well as L writes to the RAM of L + l bit. These latter writings are not potentially expensive since the memory size is small and since the frequency of non-correspondences is usually kept small. If a log file is used, these writes may be even less expensive in power. The chain backup block of Figures 5A and 5B operates in response to a number of control signals generated by other circuitry not illustrated in detail. The control signals are as follows: * reset: General reset signal to readjust some of the logic circuit. "beststate: This signal is obtained from ACS 138 (Figure 4) and indicates the state with the lowest error metric for the last process cycle The beststate signal changes before the start_chain and after the impulses from done_cha i nba ck.m decision bit: Generated in the ACS, this is the data that will be stored in the chain backup RAM. »start_chain: Impulses at the beginning of each process cycle to indicate that a backup operation can begin chain. "done_chainback: Impulses at the end of the process cycle when the chain backup operation is completed. "enable_cache_read: Allows the L + L bit, or small log file, to be used to get the output bit.The enable_cache_read signal boosts for a simultaneous clock cycle with the first boost pulse of each process cycle. cbread: Impulses L times each process cycle to perform L readings from the chain backup RAM The first one is presented after start_chainback and the last one is presented before done_chainback If there is a correspondence, only the first reading will be made, and the rest will be masked by the circuit cbwrite: Each time it pushes a decision bit that is ready to be stored in the chain backup RAM chram_addr: The normal address that will trigger the chain backup RAM For additional energy savings , these lines can be masked and kept static when the remaining readings of the backup string in Ll chain are skipped. do_compare: Internal signal that indicates that the The results of the comparator will be considered, that is, the chain-backing block compares the current value of the encstate to the beststate of the last processing cycle, saved as last_beststate, and makes the determination whether a correspondence is made or not. match: Internal signal indicating that the current value of encstate corresponds to last_beststate of the previous process cycle. m mismatch: Internal signal indicating that after the first reading of the chain backup RAM, encstate does not correspond to last_beststate. 'cbread_muxed: An internal signal that resembles cbread except that it is masked when a correspondence is made. "read_last_bit: An internal signal that is used to wax the output bit of the L + 1 bit RAM in a register." chram_dout: internal signal that is the read bit of the backup RAM in chain. "decoded output bit: The decoded output bit, is identical to the final bit that will have been produced from the completion of the complete chain backup operation of each process cycle, although its synchronization may differ. Figures 6A and 6B illustrate an implementation similar to that of Figures 5A and 5B but where a shift register of L bits is used instead of the combination of the RAM of L + 1 bit and the ascending-descending counter. More specifically, the chain-backing block of Figures 6A and 6B includes a chain-backed RAM 302, of the L-bit change register 305, and an interconnected change register 308 together with several registers and logic gates as it shows. After the first reading in a process cycle, the read bit is changed in the change register 308, the output of which is in cs ta te. If in this case it corresponds to the t_bets, the read bit is changed in the upper bit of the change register of L bits and the lowest bit of the change register of L, bits is the output bit that will result of the chain backup operation. If in this case it does not correspond to the s t_bes ts ta e, then the read bit is changed in the lowest bit of the change register of L bits and the remaining L-1 reading bits are changed in the lowest bit as well. It is pointed out that the change register of L bits needs to be able to change in both directions, that is, the change register of L bits of Figures 6A and 6B differs from a normal change register since it includes an additional input l eft which determines the direction to change. Also, for each bit read from the chain backup RAM, all L bits need to be changed once they can increase the power consumption with respect to the implementation of Figures 5A and 5B. In yet another embodiment (not shown), the use of power is further reduced by adding the decoding logic circuit to select each bit separately, with each bit of the shift register that can be loaded separately. Then, when L bit are to be stored, storage is achieved by loading each bit individually. Therefore, the registration only needs to change when the correspondences are presented (once per process cycle) thus reducing the energy consumption. In still other embodiments, circuitry is provided to verify the correspondences after the first two or more readings of a process cycle to further increase the likelihood of a match, thereby further reducing decoding time and power usage. or energy. This circuitry can be used in the embodiments of Figures 5A and 5B or Figures 6A or 6B and in other embodiments as well. In the implementations described so far, the chain back-up circuitry operates on each cycle of the process to perform a chain-back reading before deciding whether to use the cache or not to end the chain-back operation. Figure 7 illustrates an alternative implementation where chain-back readings are performed in each process cycle before deciding whether or not to use the cache to terminate the chain-back operation. More specifically, Figure 7 illustrates the circuitry used to generate the ma tch signal based on the m readings. The circuitry of Figure 7 can be employed within the cached chain back-up blocks of either Figures 5A and 5B or Figures 6A and 6B as a substitute for the circuitry that generates the corresponding ma t ch signal, shown in FIG. the same. The ma tch circuitry of Figure 7 operates in a process cycle to perform back-up readings in a chain, then to compare the current value of cs tate versus saved enstate after m-1 readings during the previous cycle of process. In this modality, the signal ena_e_ca che_read is synchronized so that it is driven simultaneously with the mth string reading. Also, instead of saving the bests value at the beginning of each chain backup operation, the value of in cs ta te is saved after m-1 readings. The particular choice of m comprises an exchange between the number of readings (m) required in each process cycle against the probability of a correspondence. A large value of m increases the chance of a correspondence after m readings. It should be noted that the circuitry of Figure 7 receives an additional signal for use in the enclosure of the room after reading. Also, the do_compa re signal differs slightly from the previous description because it is driven after m readings instead of after an individual reading and is also used to enclose itself in the value of in cs ta enclosed during the previous reading to be available for comparison during the next process cycle. In yet another more general implementation, instead of verifying the value of the test after 1 or 2 readings, in each process cycle, in this case it is compared after a to b in readings, that is after To back-up readings in chain, the value is compared to the value saved in the previous cycle of the process after a-1 readings were made then after the next reading (a + 1), encstate is compared with the value of cs ta saved during the previous process cycle after they close to readings, etc., until b readings are made in this process cycle. With this implementation, the values of in cs ta te with respect to b-a + 1 states are stored preferentially using a change register. Each successive value of this is simply a change left from the previous value of in cs ta te with a new LSB. The enabl e_ca che_read signal is asserted over a range of back-up readings in chain, stopping after b readings or once a match is found. The choices of a and b allow exchanges in terms of complexity and energy savings. The Emblems ~ of Figures 5A and 5B or Figures 6A and 6B correspond to the case where a = l and b = l, where a reading is made, therefore the circuitry quickly makes a decision whether a correspondence is presented or not. The implementation described above, where m readings are performed corresponds to the case where a = m, b = m, where it takes m readings to be the comparison. The particular choice for a and b for any given system is based on the type of system, the statistics of when convergence is likely to occur (ie, how many readings are typically needed to converge to the route read in the previous process cycle), the complexity of the physical equipment, and the desired energy requirements. To reduce the complexity of the physical equipment, a-b must be small. To reduce the power or energy requirements, a must be small and the value of b will depend on the system statistics. In general, the higher the value of b, the more likely you will find a match. In still other implementations, chain backup operations are performed on multiple process cycles. In the previously described implementations, to have a clarity in the description of the invention, it was assumed that a chain backup operation is performed in each process cycle. However, each implementation can be modified to perform chain-back operations over multiple process cycles. For example, in an implementation where a chain backup operation is presented in every 4 processing cycles, and where the result of this operation is to produce 4 decoded bits, enabl e_ca che_read could be triggered to drive only in the 4th backup reading in chain. Nevertheless, there is no requirement that this system necessarily be configured to have the enabl e_ca che_read impulse only in the fourth reading of the chain backup. Rather, if the chain backing operation was presented over 4 processing cycles, the determination of when to compare in this can still be governed by the values of a and b ,. In this regard, enable_ca che_read could assert 4 bases if a match was found resulting in 4 bits of decoded data that are read from the cache. A slightly different implementation operates to process using 4-bit slices (or any other appropriate size of chunks). So when a chain backup operation is performed, the system checks after 4 readings if a correspondence is presented. If so, the system reads the last 4 bits of the cache and transfers them, otherwise the system keeps the chain backup and stores the last 4 readings of the backup RAM in chain. Many of the implementations described so far refer to the traffic channel systems where information is processed in packets, in other words, a block of data is coded convolutionally and trailing zeros are added at the end to readjust the state of the data. encoder between each package. As a result, the system expects L + K process cycles, then the backup and chain starts and then, at the end, the system performs a final backup operation on a chain that produces L + K bits. Other implementations of the invention are suitable for traffic channels without packets such as synchronization or radio-location channels defined under IS95. For traffic channels without packets, the data is framed but the state of the encoder is not reset between each frame. So the decoder performs a chain backup operation in each process cycle. It should be understood that the principles of the invention can be exploited in almost any Viterbi decoder in series, to pass the channel type of the complete system. The exemplary embodiments have been described mainly with reference to the diagrams illustrating the elements of the apparatus. Depending on the implementation, each device element, or portions thereof, can be configured in the physical equipment, computer program, program, computer installed in circuit or combinations thereof. It should be noted that in some cases all the components necessary for the complete implementation of a practical system are not described, or are described in detail. In contrast, in these cases only the components necessary for a complete understanding of the invention have been illustrated and described. Finally, the foregoing description of the preferred and exemplary embodiments is provided to enable any person skilled in the art to make or use the present invention. The various modifications to these modalities will be readily apparent to those skilled in the art and the generic principles defined herein may be applied to other modalities without the use of the inventive faculty. In this way, the invention is not intended to be limited to the modalities shown herein but will be in accordance with the broader scope consistent with the principles and new features described herein.

Claims (14)

1. NOVELTY OF THE INVENTION Having described the present invention, it is considered as a novelty and, therefore, the content of the following CLAIMS is claimed as property: 1. In a serial Viterbi decoder for decoding a convolutionally decoded stream of symbols using a chain backup memory that stores a plurality of decision bits for each of a plurality of process cycles, an improvement comprising: a chain-backed cache, connected to the chain-backed memory, for storing a sequence of decision bits determined during a previous process cycle.
2. 2. A Viterbi decoder in series, comprising: means for receiving a convolutionally coded stream of symbols; means for generating a plurality of decision bits from the convolutionally encoded stream of symbols during each of the plurality of process cycles; a chain backup memory means for storing the plurality of decision bits for each of the plurality of process cycles, wherein the means for generating the decision bits determines, during each new process cycle, a decision bit representative of a better state metric when starting with a current start metric of better status and then performing a sequential backup chain operation through the plurality of decision bits stored in the chain backup memory medium for each of the plurality of process cycles; and a chain-backed cache means, connected to the chain-backed memory means, to store a sequence of decision bits accessed during a previous chain-back-up cycle and to transfer the decision bit that would otherwise have been generated.
3. The Viterbi serial decoder according to claim 2, wherein the chain backup cache means comprises: a means for storing the metric of best condition for the previous process cycle; a means for storing the sequence of access decision bits during the previous process cycle; a means to receive the best state metric for the current process cycle; and a means to compare a changed version of the best-state metric for the current process cycle to the best-condition metric of the previous process cycle and, if there is a match, to transfer the most previous decision bit stored by the means to store the sequence of decision bits accessed during the previous chain backup operation.
4. The Viterbi serial decoder according to claim 3, wherein the chain backup anti-memory means operates to perform a to b readings during each process cycle, wherein after readings, the anti-memory means is verified for each subsequent reading until b readings have been made or until a match is obtained.
5. 5. The Viterbi serial decoder according to claim 4, wherein a is m and b is m.
6. The serial Viterbi decoder according to claim 4, wherein a is 1 and b is 1.
7. The Viterbi serial decoder according to claim 2, wherein the chain backup anti-memory means comprises: a closure for storing the best condition metric for the previous process cycle; a change register left to receive the best-status metric for the current process cycle; a comparator to compare the best-state metric for the previous process cycle to a changed version of the best-state metric of the current process cycle and if there is a correspondence to transfer a correspondence signal; and a RAM of L + 1 bit to store the sequence of decision bits accessed during the previous chain backup operation, where L is the chain back-up length; an output circuit, connected to the RAM of L + l bit and the comparator, to receive the signal of chain backup of the comparator and to control the RAM of L + l bit to transfer the earliest stored bit to it.
8. The serial Viterbi decoder according to claim 2, wherein the chain backup anti-memory means comprises: a closure for storing the metric of better state for the previous process cycle; a change register left to receive the metric of better status for the current process cycle and for the change of the decision bits; a comparator to compare the metric of better state for the previous cycle of the process to a changed version of the metric of better state of the current process cycle and if there is a correspondence, to transfer a correspondence signal; and a change register of L bits to store the sequence of decision bits accessed during the previous chain backup operation, where L is the chain back-up length; an output circuit, connected to the change register of L bits and to the comparator, to receive the correspondence signal from the comparator and to control the change register of L bits to transfer the earlier decision bit stored therein.
9. 9. The Viterbi serial decoder according to claim 2, wherein the chain backup antimemory means comprises: a change register left to change the best state metric for the current process cycle; a plurality of sequential registers for storing previously changed versions of the best-status metric; a comparator for comparing an output of the shift register left to, an output of at least one of the plurality of sequential records and, if there is a match, for transferring a matching signal; and a RAM of L + 1 bit to store the sequence of decision bits accessed during the previous chain backup operation, where L is the chain back-up length; an output circuit, connected to the RAM of L + l bit and the comparator, to receive the chain backup signal from the comparator and to control the L + 1 bit RAM to transfer the earlier decision bit stored thereto.
10. 10. A method for performing Viterbi decoding in series, comprising the steps of: receiving a convolutionally coded stream of symbols; generating a plurality of decision bits from the convolutionally encoded stream of symbols during each of the plurality of process cycles; storing the plurality of decision bits in a chain backup memory for each of the plurality of process cycles; determining, during each new process cycle, a decision bit representative of a better state metric when starting with a current start metric of better state and then performing a sequential chain backup operation through the plurality of bits of decisions stored in the chain backup memory medium for each of the plurality of process cycles; and storing a sequence of decision bits accessed during a previous chain-back operation in a chain-backed antimemory and storing the decision bit that would otherwise have been generated by the sequential chain-back operation if a changed version of The metric of better state for the new process cycle is the same as the metric of better state of the last process cycle.
11. The method according to claim 10, wherein the step of storing a sequence of accessed decision bits during a previous chain-back operation in a chain-backed antimemory and transferring the decision bit representative of the best-state metric if the current metric of better state for the new process cycle indicates the start metric of the last process cycle, it includes the steps of: storing the best state metric for the previous process cycle; store the sequence of decision bits accessed during the previous chain backup operation; compare the best state metric for the current process cycle; and compare the metric of better state for the previous process cycle to the metric of better changed state of the current process cycle and if there is a corospondence, to transfer the earlier decision site stored by the medium to store the sequence of data bits. decision accessed during the previous chain backup operation.
12. 12. The method according to claim 11, wherein the step of storing a sequence of decision bits accessed during a previous chain-back operation in a chain-backed antimemory and transferring the decision bit representative of the best-state metric if the Current metric of better state for the new process cycle indicates the start metric of the last process cycle is controlled to perform from a to b readings during each process cycle, where after the readings, the antimemory means is verified for each Subsequent reading until and b readings have been made or until a correspondence is obtained. The method according to claim 12, wherein a is m and b is m. The method according to claim 4, wherein a is 1 and b is 1.