MXPA00009043A - High speed signaling for interfacing vlsi cmos circuits - Google Patents

Abstract

A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using XOR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs. The system may use a first set of oscillating references on a first bus for detecting transitions in control information and a second set of oscillating references for detecting transitions in data information.

Description

HIGH SPEED SIGNALING TO INTERFASE CIRCUITS OF VLSI CMOS BACKGROUND OF THE INVENTION __ _ Field of the Invention This invention relates, generally, to the communication of computer signals and, more particularly, to an integrated circuit interface and method for the transfer, in high-speed blocks, of signaling. of data, of control signals and direction between multiple integrated circuits on a collector or from one point to another, with reduced energy consumption. Description of the Prior Art _ __ Semiconductor integrated circuits, used in digital computing and other digital applications, often use a plurality of interconnected circuits of Very Large Scale Integration ("VLSI7? T to carry out binary communication through one's transmission lines. or multiple segments.The conventional transmission lines include traces, which are formed on a suitable substrate, such as a printed circuit board.Each transmission line can be designated, for example, using the so-called traces of micro-strips and traces of belt lines to form a transmission line that has a characteristic impedance of the order of approximately 50 to 70 ohms Alternatively, each transmission line may have its opposite ends terminated in their characteristic impedances The output load on a drive impeller such a transmission line can be as low as 25 to 35 ohms. Reasonably, high-frequency signaling requires signals of small amplitudes. For a receiver to detect voltage oscillations (for example, from 0.8 to 1.2_V) easily in a noisy environment, such as GTL, HSTL, SSTL or RAMBUS, the current must also be very large (for example, of the order of 50 to 60 milliamps per controller). A typical receiver uses a comparator with a voltage reference signal ("VREF") set halfway between the high input voltage ("HIV") and the low input voltage ("VIL"). The VREF signal is a high impedance DC voltage reference ("DC"), which tracks freely with power supplies over time, but can not respond to instantaneous noise.

Conventionally, the High Output Voltage ("VOH") and the Low Output Voltage ("VOL") denote signals that emerge from the transmission source, and the VIL and VTH "denote signals arriving at the input of the receiving device, although they can be considered the same signal Figure 1A is a block diagram illustrating a prior art receiver 10, which uses RAMBUS technology The system 10 includes a cushion "100 coupled by signal rings 103 to" internal input receivers A VREF signal 105 is "coupled to each internal receiver 110. The VREF is generated from the power supply. Usually, the DC value of the power supply varies by five percent (5%). Figure IB is a timing diagram 125, illustrating an example signal relating to a high reference voltage ("VREFh") and a low reference voltage ("VREFl"). The values of the VREFh "and VREFl typically depend on the variation of the power supply used to generate the VREF signal.The oscillation of the large voltage, ie the difference between a high voltage signal (" "HIV") and "the signal low voltage ("VIL") and stable signal levels above and below the VREF signal are required for ^ reliable detection of signal polarity. * Voltage oscillation of current single-ended signaling technologies * is conventionally around 0.8 V. Fig. 1C is a block diagram illustrating schematic shapes of a receiver 150 deH the prior art, using RAMBUS technology, the receiver 150 sampling the level of the input signal 167 and the signal 154 of the VREF until this signal reaches a stable level, at the time it passes gates 160 and 165 it is cut off. Once the gates 160 and 165 are passed and cut off, the detection gate 172 is enabled to eliminate the current injection. Figure ID is a time diagram 175 illustrating the operation of receiver 150 for an example signal. This receiver 150 samples the input reference and the input signal until they reach a stable level, for example, a low logic level ("VIL") and, while the input signal is stable, the receiver 150 detects the value of the input signal. As noted above, for reliable detection of the signal, the oscillation of the signal voltage must be fast enough to allow all 150_ receivers to sample a stable signal with an adequate margin for adjustment and retention time. This voltage oscillation must occur in less than 30% of the minimum cycle time to allow for margin for signal deviation, adjustment and retention times. As the minimum cycle time is reduced below 1 nanosecond, the margins are reduced for the signal deviation, set-up time and retention time, with the additional load on the impeller current in an operation of the high-capacitance high-frequency charging environment. LVDS ") used by the IEEE P1596.3 can overcome these problems, using a voltage oscillation of 250 mv at the expense of the operation of the complementary signals. The operation of complementary signals inevitably increases the number of pins and the size of the package . ~~ In addition, computer systems typically use a collector system, in which several devices are coupled to the collector, most of them use a clock to validate idar data, direction and control signals. Figure 21 illustrates a prior art system 2100 for the DRDRAM, which uses a clock line 2130, which has two segments, 2136 and 2138. A segment 2136 extends from one end of the data collector to a change point 2137 of position, near the second end of the collector. The other segment 2138 of the clock extends from the position change point 2137 back to the first end of the data collector. The signal collector 2120 carries data and direction and control signals. This topology ensures that a signal sent over the collector 2120 always travels contemporaneously with and in the same direction as the clock 2132 used by the device to receive the signal. This works well if the load shifts all the signals and the clock is almost identical and the clock 2132 is used for the sample and reception of the signal. However, sometimes the system may require double the data bandwidth, in this case this type of collector system needs to double the number of signals, although the directional signals? of control are identical and could have been shared. _ _ Therefore, there is a need for low-power controllers and reliable receivers for the high-frequency operation of a large number of single-ended signals in existing technology for low-cost digital VLSI systems.

COMPENDIUM AND OBJECTS OF THE INVENTION A system of the present invention uses small synchronous voltages of oscillation differential source and chronometric reference signals ("SSVTR and / SSVTR) to compare single end signals of the same oscillation, generated from the same integrated circuit for the High frequency signaling It will be appreciated that "/" is used to indicate a logical "NO." All signals are terminated with their characteristic impedance at both ends of the transmission lines.The SSVTR and / SSVTR tilt each time the signals Valid are driven by the integrated transmission circuit Each signal receiver includes two comparators, one to compare the signal against the SSVTR and the other to compare the signal against the SSVTR.A binary value of the present signal determines which comparator is dock, optionally using the exclusive O-logic with the SSVTR and / SSVTR, until Xas SSVTR and / SSVTR have changed their value or binary, the comparator coupled to the receiver detects whether a change in the binary signal value occurred. Again, it will be appreciated that the SSVTR and / SSVTR change their binary value each time the signal can change its binary value. The SSVTR and / SSVTR are preferably synchronized with the signal. The method of the present invention includes the steps of obtaining an oscillation source synchronous voltage and the chronometric reference ~ and its complement (SSVTR and / SSVTR), and receiving an incoming single end signal.The method compares the oscillation reference against the signal that enters a first comparator, to generate a first result, and compares the complement against the input signal by a second comparator, to generate a second result.The method then selects one of the first result or the second result, As an output signal based on the previous signal, the step of selecting one of the results includes comparing the output signal to the reference (SSVTR) and the complement (/ SSVTR). output of the previous signal to the first result or the second result, based on the comparator, which is currently engaged.If the input signal changes, the "de" stage lesson includes keeping the same comparator attached. If the input signal remains the same, the selection step includes uncoupling the currently coupled comparator and coupling the other comparator. The method then allows e? circuit stabilizes. - The system and the method advantageously eliminate the need for a high impedance VREF signal for the comparison of the low end simple oscillation signals. This reduces the need for three different voltage levels (the high output level, the low output level and the VREF level) to two different voltage levels (the high output level and the low output level). Eliminating the VREF reduces the necessary voltage oscillation and, therefore, reduces energy consumption. Using a receiver with double comparators, allows the coupling of the receiver to the same comparator, when the signal changes each cycle. Only one comparator is coupled based on the binary current value of the signal and the SSVTR. The system has a delay, individually adjustable, so that each receiver is coupled or decoupled from the comparator, thus reducing the effect of the deviation during the transmission of the synchronous signals from the source. "The system can have multiple synchronous source voltage and chronometric reference signals to compare multiple signals, single ended on the same integrated circuit, such as a microprocessor controller or system that has many signals." The system and method provide benefits of Differential signaling in a single-ended signaling system - Using the same concept, the system has signals of synchronous voltage of complementary source, bi-directional and oironometric reference signals, to compare bidirectional single-ended signals. The system may have an impeller or transmitter to control the rate of signal deviation which will be a substantial portion of the total signal period, thereby reducing the output current.The system may have a matching internal impedance circuitry, such as positive coupling resistors or ground gate p-channels, for correspondence of the characteristic impedance of the transmission line at both ends of a point-to-point connection between the Peripheral Control Unit (CPU) and the cache memory (fast memory) ) and the CPU and the system controller The system has a double comparator circuit to convert a single-ended collector with two complementary signals to be transmitted and received with comparable noise immunity from the differential collector for the internal data collector. memory, the processor or other integrated circuits of wide data collector type. It is possible for a transmitter device size with a slow on and slow off to have similar deviation regimes for all the signals in each group of SSVTR and / SSVTR and the plurality of signals that "are transmitted together. Furthermore, it will be appreciated that the control signals and the direction signals may be transmitted in a different channel than the data signals. This operation enables the control and direction channel on a different frequency than the data channel, and enables different loads to be applied to each of the channels.

BRIEF DESCRIPTION OF THE DRAWINGS Figure IA is a block diagram illustrating the RAMBUS base receiver of the prior art; Figure IB is a synchronization or chronometric diagram illustrating the signal levels of the receiver-of the prior art of Figure IA; Figure 1C is a schematic diagram, illustrating another RAMBUS base receiver of the prior art; Figure ID is a chronometric diagram showing the operation of the prior art receiver of Figure 1C; Figure 2A is a block diagram illustrating a system with master and auxiliary devices, in accordance with the present invention; Figure 2B is a block diagram illustrating the system of Figure 2A, which has transmission lines with impedance matching resistors at the ends; Figure 3A is a timing diagram illustrating differential reference signals SSVTR and / SSVTR relating to signal detection times; Figure 3B is a timing diagram illustrating the SSVTR and / SSVTR relative to the single end signal; Figure 4 is a schematic high-level view, illustrating the single-ended signal receivers; Figure 5 is a flow chart illustrating a method of communicating signals from a transmitter, through a transmission line to a receiver; Figure 6A is a schematic diagram illustrating the slow-on and slow-off controller for all signals; Figure 6B is a schematic diagram illustrating controllers having adjustable rates of signal deviation and this deviation between signals; Figure 7A is a schematic diagram illustrating a single end signal receiver of Figure 4 in a first embodiment; Figure 7B is a schematic diagram illustrating a single-ended signal receiver in a second embodiment; "" ~ "~ ^ Figure 7C is a schematic diagram illustrating a single-ended signal receiver of Figure 4, in a third embodiment, Figure 7D is a schematic diagram illustrating a single-ended signal receiver of the Figure 4, in a fourth mode; Figure 8A is a schematic diagram illustrating the details of the comparator circuit SSVTR a / SSVTR of Figure 4; Figure 8B is a schematic diagram illustrating the details "" of the comparator circuit / SSVTR to SSVTR of Figure 4; _ _. Figure 9 is a schematic diagram illustrating receivers with individually adjustable delays to eliminate deflection during transmission; - Figure 10 illustrates a waveform of the signal and the deviation between them, - Figure 11 is a perspective view of the hard wiring arrangement of the system of Figure 2; Figure 12A is a block diagram illustrating a system from one point to another, in "accordance with this" invention; "" Figure 12B is a block diagram, illustrating the connection from one point to another of Figure 12A, which has gateway p-channel devices, which coincide in impedance, within the integrated circuit; Figure 13A is a block diagram in a perspective view, illustrating a unidirectional signaling system and a bidirectional signaling system, in a simple integrated circuit; Figure 13B is a block diagram in a perspective view, illustrating four signaling systems on a simple integrated circuit; Figure 14A illustrates a fixed voltage reference of the prior art, whose value is around the midpoint of the logic high voltage level and the logic low level; Figure 14B illustrates complementary references having the same voltage oscillation co or any signal, - Figure 15A illustrates a differential amplifier that amplifies the difference between a data signal and a reference; ~~ Figure 15B is a block diagram illustrating the address logic; - - Figure 16 is a circuit diagram illustrating a receiver of single-ended signals, with differential amplifiers guided by a power or signal damper that enables a receiver to disconnect power to the receiver when not in use; Figure 17 is a timing diagram illustrating the signal transition time in an application that requires the change of position of the fast collector from read to write, or vice versa; "" "Figure" 18 is a block diagram illustrating a system from one point to another; Figure 19 shows a system having multiple collectors, where the signals are received simul- anally; Figure 20 is a diagram ie blocks, which illustrates a system having three collectors, to achieve greater bandwidth; and Figure 21 illustrates a prior art system for DRDRAM memory, which uses a clock line having two segments.

DETAILED DESCRIPTION OF THE PREFERRED MODE - The present invention provides a signaling system and a method for high-speed communication over multichannel collectors or connections from one point to another, between multiple "VLSI" devices and sumimstra a lower power consumption in relation to the current methodology of communicating single-ended signals The signaling system can be used to connect multiple memory devices with a "multi-channel" collector to a memory controller for the transfer of data blocks, addresses "and control information Using multiple collectors, such as DRAMs, cross-point switches, processors, broad SRAMs and system controllers can be placed together to achieve bandwidths of up to four gigabytes / sec. Virtually all the signals needed for Aunt Computer or other digital systems can be sent in this collector. Those skilled in the art will recognize that all devices, such as PCUs in the computer system, need the methodologies and collector structures of this system. Figure 2A is a block diagram in a perspective view, illustrating a system 200 with a master device (transmitters) 205 coupled by means of the collector architecture (transmission lines) 215 to multiple slave or auxiliary devices (receivers) 210, in accordance with the present invention. An example of a pair of a master device 205 and a slave device 210 includes a microprocessor and system controller, or a memory controller and memory device (e.g., DRAM). As illustrated, the master device 205 is configured to communicate, for example, twenty (20) signals that include the signals from single-ended SO to S17, synchronous source voltage r'ompJ small oscillation and chronometric references, SSVTR and / SSVTR, power lines (not shown) and ground lines (not shown) parallel to the transmission lines 215 of each slave device 210. It will be appreciated that "/" is used to indicate a logical NO. S17 may be data, control or addresses, or multichannel or non-multichannel, as defined by the piotocol There may be additional signals, such as clock or initialization, for other purposes required by the protocol or system synchronization. "~ As shown in Figure 3A, the SSVTR and / SSVTR signals tilt each time the valid signals are driven by the master device 205. It will be appreciated that the slave device 210 may include multiple receivers (405, Figure 4), in which each receiver 405 includes two comparators, one to compare the signal against SSVTR and the other to compare the signal against / SSVTR. A present signal binary value determines which comparator is coupled to the output terminal 420, optionally using the exclusive O-logic with SSVTR and / SSVTR. Until SSVTR and / SSVTR have changed their binary value, the enabled comparator in receiver 405 detects whether the change in the value of the binary signal occurred. For chip-to-chip communication (microcircuit to microcircuit) on a manifold or point-to-point, all "signals are preferably transmitted substantially at the same time from the same chip to another chip or plurality of microcircuits or chips connected on the collector and they have preferably the same charge, oscillation and deviation regime (when the signals are in transition). Likewise, for intra-chipping communication, the signals are preferably driven at the same time, substantially, from the same area or block to other areas or other blocks, on the same chip and preferably have the same load, oscillation and rate. deviation (when the signals are in transition). Figures 19 and 20, described below, illustrate a system and method for ensuring that the signals are driven substantially at the same time. "" " To facilitate extremely high data transmission rates in this external collector, collector cycles are initiated when SSVTR is low (ie, / SSVTR is high). All block transfers begin during the cycle when SSVTR is low and end with SSVTR going low to easily preset receiver 405 for the last binary value of the signal. This allows discontinuous transfers of even numbers of bits. When the signals need to change direction (due to the channeling nature of the signals), one or more inactive cycles may be required to establish the collector, due to propagation or establishment delays of SSVTF and / SSVTR, when they are bidirectional . Figure 17, described below, illustrates the bi-directional moment for the collector to turn around to avoid lost idle cycles. Figure 2B is a block diagram illustrating system 200 (Figure 2A) having transmission lines 215 with external impedance matching resistors 220, having the terminating resistance equal to its characteristic impedance, which is preferably between 50 and 70 ohms, at the ends. The termination voltage of * is labeled as VTT, which is preferably around 1.8V for an operating voltage of 2.5V (for VCC of 2.5V and VSS of OV). The oscillation of the nominal voltage is preferably set to less than one volt, preferably less than 40% of the supply voltage, and more preferably it is adjusted to 500 mv. Therefore, as shown in Figure 3A, the high output voltage (VOH) is 1.8 V and the low output voltage (VOL) is 1.3V. Figure 3A is a timing diagram illustrating the complementary reference signals SSVTR and / SSVTR in relation to signal detection times. SSVTR starts at VOL and / SSVTR starts at VOH. In the first cycle, the master 205 drives all the signals going low, which include / SSVTR, to VOL at the same time and the terminating resistors 220 raise SSVTR- to VOH. The single-ended signals that are high are held in VOH by the terminating resistors. The appropriate detection time, that is, the time to * detect the logical level of an input signal, is then the transition junction of SSVTR and / SSVTR and before the stable time, that is, when SSVTR or / SSVTR reaches the Stable status in HIV or in VIL. The SSVTR and / SSVTR preferably have equal times of rise and fall, in which each time of rise and fall is approximately half of the cycle time of any reference. Figure 3B is a timing diagram illustrating SSVTR and / SSVTR in relation to the single end signal. The single-ended signal starts at / SSVTR at a high voltage, and then changes coriT / SSVTR at a low voltage. The single-ended signal then remains at a low voltage, thus becoming equal to SSVTR and then changing with SSVTR to a high voltage. The single-ended signal then remains at a high voltage, thus becoming equal to / SSVTR. Figure 4 is a schematic high-level view, illustrating a single-ended signal slave device 210, having a receiver 405 for each signal line 215. Each signal receiver 405 has two comparators 410, a comparator 410a for comparison a single end signal entering, "SNx" or SSVTR and the other comparator 410b to compare SNx to / SSVTR. Both comparators 410 have output terminals selectively coupled by the switches 415 to an output terminal 420. It will be appreciated that the output signal (SN) to the output terminal 420 is preferably a complete rail signal (OV at 2.5V). As indicated before, the SSVTR is initially adjusted to VOL and the / SSVTR and SNx are initially adjusted in VOH. SN is initially adjusted to a full rail high output voltage. Therefore, comparator 410a amplifies high voltage SNx minus low voltage SSVTR, thus providing a high output signal. Comparator 410b amplifies the high voltage SNx minus the high voltage SSVTR, supplying an unknown amplified signal in noise. The selection of switch 415 is controlled by logic gates 425 of exclusive O-logic (X0R) _. More particularly, gate 425a XOR compares an amplified signal (VT) of full rail SSVTR against the output signal SN and generates a control signal to control the breaker 415a. The gate XOR 425b compares / full rail SSVTR (/ VT) against the output signal SN, and generates a control signal to control the switch 415b. In this initial state, only SSVTR and, therefore, VT are low, thus causing XOR 425a to push switch 415a to the closed state. Accordingly, the output of the comparator 410a (high) arrives at the output terminal 420. XOR 425 drives the switch 415b to open, thereby preventing the entry of the unwanted output signal from the comparator 410b. The receiver 405 is stable. Following the example illustrated in Figure 3B, the single-ended SNx signal changes at low voltage. As always, SSVTR and / SSVTR change opposites to each other. Therefore, as soon as SSVTR and / SSVTR achieve a predetermined difference (preferably 250 mV) between them, VT and / VT make the transition. Similarly, as soon as SSVTR and SNx change to a predetermined difference (preferably 250 mV), among them, the output of the comparator 410a also changes (at a low output voltage). It will be appreciated that the path from the external signal SNx to the generation of the output signal STT and the trajectory for the generation path of VT and / VT of the complete rail signal, each one includes "a comparator 410 or 435 and two inverters 430 or 440. Thus, each XOR 425 will receive new input signals based on the comparison speed by comparators 410 and 435. In this example, as is evident from the example timing diagram of Figure 3B, SSVTR and / SSVTR will achieve a predetermined difference at the same time that SSVTR and SNx achieve the same predetermined difference.Therefore, the XOR 425a will continue to receive differential inputs, thus keeping the same switch 415 closed and enabling the low output voltage of comparator 410a to pass. to the output terminal 420. The receiver 405 is still stable __ Following the example of Figure 3B, the single-ended SNx signal does not transition, as always, SSVTR and / SSVTR make "transition in mutual relationship. therefore, comparator 410a currently enabled continues to drive the low output voltage. When SSVTR and / SSVTR achieve a predetermined difference in mutual relation, but before SSVTR reaches the same voltage as SNx (thus avoiding the possibility of an undetermined state of the output signal), the XOR 425a is disconnected and "the XOR 425b It will be appreciated that, since the SSVTR starts to rise, the comparator 410b can drive a low output voltage The receiver 405 is still stable Each receiver 405 can easily detect and amplify very small signals, of the order 100 to 250 mV7 If the transition has occurred in the single-ended SNx signal, the output signal SN has the new level opposite its previous signal level, since both SSVTR (or / SSVTR) and the single-ended signals have made transition, the same comparator 410 is still coupled to the signal output terminal.If the single-ended SNx signals have not transitioned, then the SN signal output will not change, the comparator 410 will side ~ at the start of the transition it is decoupled from the output, after the SSVTR and / SSVTR receiver has amplified its new binary state (VT and / VT). and the other comparator 410, which has the opposite SSVTR (or SSVTR) is coupled to supply the signal output. The old output level is thus restored. It will be appreciated that the receiver 405 can be realized without using the XORs. This can be achieved by using the known polarity of SSVTR and / SSVTR in the initial cycle and all single-ended signals start high. The transition of SSVTR and / SSVTR is made in each cycle. Thus, its polarity in each cycle can be determined by examining - the system clock in a synchronous system "- and defining the start of the cycle in the even cycles of the clock (ie SSVTR is low in the clock cycle pair and / SSVTR is High) Then, only the output signal "SN" is monitored to couple and uncouple the comparators 410 based on whether the output signal SN changes state each cycle or not_ If the output signal SN changes state, the comparator-coupling is left alone If the output signal SN does not change, the coupled comparator is decoupled and the other comparator is coupled, etc. It will also be appreciated that a system, embodying the invention, makes it possible for all signals to be connected to low impedance sources, enables all signals to present voltage and noise conditions, virtually similar to differential signals in noise immunity, and enables the reduction of voltage oscillation in compassion with other s Single-ended signaling technologies, such as RAMBUS, HSTL or GTL. "" The small 0.5V oscillation performed in this exemplary mode, allows very low signal regimes, with much lower power consumption, compared to the other existing single end signaling technologies. In addition, it will be appreciated that each receiver 405 amplifies the single-ended SNx signals during the transition of the signals without the need for a conventional clock or other time signal, except SSVTR, / SSVTR and its amplified versions, VT and / VT. Figure 5 is a flow diagram illustrating a method 500 for communicating signals from a master 205 ~ * through a transmission line 215 to a receiver 405. Method 500 starts with master device 205 in step 505 which adjusts SSVTR to VOL and all single-ended signals (/ SSVTR and SNx) to VOH, and "in step 5Í0 adjusts all outputs of the single-ended receiver (SN) to a high full rail. The receiver 405 in step 515 couples the comparator 410a, which compares SSVTR against each single-ended SNx signal, to the output terminal 420 of the receiver 405. This receiver 405 in step 517 allows all signals in the transmission lines settle down Steps 505-517 are referred to as system initialization. The master device 205 in step 520 simultaneously drives SSVTR and / SSVTR to its opposite states and all single-ended SNx signals at * their desired levels. The receiver 504 in step 530 compares the single-ended SNx signal against SSVTR and / SSVTR in the respective comparators 410. The receiver 405 in step 540 determines whether there is transition of the single-ended signal. If so, then the receiver 405 in step 545 passes the result to the output terminal 420, and keeps the same comparator 410 coupled to the terminal 420"." If not, then the receiver 405 in step 550 decouples the previous comparator 410, couples the other comparator 410 to the output terminal 420 and maintains the same output signal (SN). The transmitter 405 in step 555 determines whether the signal burst continues. If so, method 500 returns to step 520. Otherwise, method 500 terminates. Figure 6A is a schematic diagram illustrating a slow-on and slow-off master 205 device for a single-ended signal in a first embodiment referred to as the transmitter 600. The transmitter 600 includes an NMOS 605 bearer device coupled to a transmission line 610, to exactly adjust the output oscillation to 500 mV below VTT. This NMOS 605 abatement device includes an NMOS abatement CT TI, having a source coupled to the transmission line 510, its discharge coupled to ground, and its gate coupled to the diversion control circuitry 620. This system of diversion control circuits 620 includes a CMOS inverter, comprising two transistors T2 and T3, coupled between two resistors R1 and R2. The input to the CMOS inverter is coupled to a signal control device 625. "For example, to generate SSVTR or / SSVTR, the signal control device 625 can be an oscillator.It will be appreciated that the amount of abatement can be adjusted using a recorder (not shown) and a spike in series (not shown") During the initialization to adjust the correct oscillation of the voltage for any variation of the process or "device." Other methods, such as the use of feedback techniques for control, are shown in the article by Hans Schumacher, et al., "CMOS Subnanosecond True-ECL outpüt buffer ", J. Solid State Circuits, Vol. 25 (1) pages 150-154 (February 1990), can also be used, maintaining the current at 20 mA, and having parallel terminations of 50 ohms in both ends of the transmission line 610 (as controlled by Rl and R2) generates an oscillation of 500 mv under all conditions, to have slow rise and fall times in the output and to minimize the reflections, the noises Switched network of signal coupling and termination ", the diversion control circuitry 665 controls the abatement CT transistor to turn on and off slowly. The preferred deviation rate is 1.6 nanoseconds / volt, with transition times from 0.8 ns to 500 mv. For a ramp-type, uniform-transition signal, the preferred rate of deviation of the signals is four times the sum of two inverter delays and an O-exclusive delay in a given technology. In 0.25 μ CMOS technology with the operating voltage of 2.5 V, the inverter delay is 50 picoseconds and the exclusive O-delay is about 120 picoseconds. Thus, the preferred deviation rate is approximately 880 picoseconds. For signals transmitted above the 600 MHz rate, the signal deviation rate is preferably less than 110% of the signal rate. This preferred deviation regime for exponential signals is slightly faster if the signal reaches 75% of its final value, earlier than 3/4 of the transition time. The differential signals preferably cross half through the voltage transition. At about 3/4 of the way through the voltage transition, the signals have a difference of about 250 mv, which can quickly become a large oscillation signal. To prevent amplification of the noise and prevent coupling of the signal to the receiver output by receiving the single-ended signals, without transition, the transition time between 75% and the value of the final signal is preferably greater than the sum of the two inverter delays and the exclusive O-delay. It will be appreciated that the deflection rate can go so fast that it takes the amplified noise to reach the output of the comparator 410, whose output is coupled to the output terminal 420. * That is, aT receive a signal without transition, the "switches" 415 change state before the comparator output - change state based on noise amplification The output of comparator 410, currently coupled, approaches an undetermined state (amplified noise) Switches 415 must change state before this "undetermined" exit becomes available. It will further be appreciated that the inequalities of devices, manufacturing tolerances and reflection of signals will affect the "speed at which the output of the buyer 410 reaches the undetermined state." As technology improves, gate delays, regimes can be achieved. of faster deviation and faster signal regimes Figure 6B is a schematic diagram illustrating the master device 205 having adjustable rates of signal deviation and deviations between the signals, in another exemplary embodiment, referred to as the transmitter 650. This transmitter 650 includes a "655 NMOS abatement device, coupled to the transmission line 610 to exactly match the output oscillation at 500b below VTT. This abatement 655 NMOS device includes parallel NMOS 660 transistors connected in parallel, each having its source coupled to the transmission line 610, its discharge coupled to ground and its gate coupled to the system of circuits 665 of deviation control. This system of diversion control circuits 665 includes a CMOS inverter, comprising two transistors T2 and T3, coupled between two with 670 and 675 resistors connected in parallel.The input of the CMOS inverter is coupled to the signal control device 625. The settings 670 and 675 of the resistor tune the rise and fall times It will be appreciated that the rise and fall times are preferably as symmetric as possible, to have the crossing of the midpoint of all the signals and to detect all these signals by differential receptors to occur simultaneously, symmetry and adjustment of the deviation regime and the Output oscillation during the test phase, by fuses (not shown) or during initialization on the board by setting a recorder (ño shown). It will be appreciated that the moments of signal transition may be slightly greater than the signal regime. In some heavily loaded collectors, the oscillation can be increased to take into account the transmission losses, still presenting 500 mv for the receiver 210 to detect easily. It will also be appreciated that several deviation regimes, exponential transition times and voltage oscillations are possible, based on the technology, receiver loading and acquisition and resolution delays. Even transition times slightly greater than the signal regime are possible with transition signals that reach 90 to 95 percent of their final value, while in bursts. Also, during the deviation test, between the single end signals and the SSVTR and / SSVTR are adjusted using the NMOS abatement size and the resistors in the gate before it, using well known techniques, such as laser fuses or adjusting the code of the recorder to achieve the waveform configuration of the signal, as shown in Figure 10. In this Figure 10, all single-ended SNx signals must be coincident or less than 50 pség in front of the transition of SSVTR and / SSVTR. "This deviation can be adjusted after testing to be in this range Figures 7A.7D illustrate alternative embodiments of each signal receiver 405 of Figure 4 * It will be appreciated that comparators 410 of receiver 405 need to operate during each cycle, requiring small acquisition and resolution delays, not taking the input current and not injecting current back into the signal lines. common_differential satisfies all these requirements. Referring to Figure 7A, the receiver 210 uses double differential amplifiers 702, a differential amplifier 702a to compare the signal SNx to SSVTR and the other differential amplifier 702b to compare the signal SNx to / SSVTR. For the complete form, a brief review of the differential amplifiers 702 is provided. The differential amplifier "702 is always enabled." Based on the channel sizes, when the SSVTR voltage is greater than the SNx voltage, more current is driven through the PMOS UNC transistor, thus extracting the output voltage at the node 707 high (near VCC or 2.5V) .When the SSVTR voltage is lower than the SNx voltage, more current is driven through the NMOS Til transistor, thus extracting the output voltage at the low 707 node (near VSS) or 0V) The differential amplifier converts the 0.5V input (small oscillation) to a large oscillation output (0V to 2.5V) The outputs of the differential amplifiers are amplified and inverted by an inverter 704, passes through the CMOS transmission gates 706 and are joined together in the node 708. The transmission gates 706 are selectively operated, depending on the amplified state of the previous signal (SN) exclusively of type O, with an amplified state of SSVTR or / SSVTR, ie VT or / VT, respectively. The O-exclusive is designed to be stable without deformations for small time variations, between SN, VT and / VT, reaching their respective logical levels. Several modalities are shown. Figure 7A illustrates differential amplifiers always-enabled, with only the transmission gates being selectively enabled for few devices and higher speeds as an alternative mode 700. FIG. 7B illustrates a differential amplifier for the transmission gates, being enabled or disabled simultaneously as the alternative mode 720. Figure 7C illustrates differential amplifiers being enabled by the same exclusive O for lower energy, the fast disabled of the transmission gates during the transition from the exclusive O-output and slow enable for transmission gates after set the exclusive-O as an alternative mode 740. Figure 7D illustrates P-channel differential amplifiers with a 1.2 V termination voltage for lower power applications, as an alternative mode 760. All the gates of the differential amplifier can be disabled for power reduction when the receiver or when the device is not selected or the device is in the deep energy descent mode. The differential amplifier can be disabled by turning off the Til transistor. Using a 1.2 V termination and the 405 * receiver as shown in Figure 7D, the power consumption can be further reduced by another 33%. That is, the oscillation of the voltage will be from 1.2 V to 0.7 V, allowing decent margins of ground rebound and lower energy consumption for portable systems. The frequency of operation can be comparable with "fewer devices in the collectors, which is common with portable devices for a smaller form factor." The transmitter 205 can still be a low-level NMOS TI or a parallel connection of Low level NMOS 660. The receiver operation is similar, except that the differential amplifier 702 becomes a mirror image, thus increasing the gate capacitance in the signals that go in the gate of the P-channel, for the comparable performance approximately twice, due to the increased size of the P-flute device. Other configurations of differential amplifiers, which convert the differential signals of small oscillations into differential signals of large oscillations rapidly, can be used alternatively, instead of the differential amplifiers shown. expert in the field will recognize that another modality can use different VTT, one p for signals equal to 1.8V with ^ 500 mv of oscillation and another for oscillating reference signals equal to 17. V with oscillation of 300 mv. All signals are transitioning at the same time and have similar times of rise and fall. The same transmitter and receiver pair can carry out the management of the multiple VTT system. It will be appreciated that the direct current (DC) orientation point of each differential amplifier in the receiver 45 is configured such that the receiver's voltage 405 is above the VCC half, when both small oscillation voltages (signal Single end SNx and SSVTR or differential amplifier enabled SSVTR) are close to HIV and below half VDC when both small oscillation voltage are VIL wax. This direct current orientation allows adequate margin and preservation of the output SN signal, when the single-ended SNx signal does not change e? state and the SSVTR or / SSVTR of the differential amplifier enabled are close to the differential signal, before they become uncoupled. Since the receiver 405 operates during the signal transition for the small oscillating single "" end signal, the concept of adjustment _ and retention time from a specified time, after the signal level reaches VT? / VIL or VREF eri "ls" previous signaling techniques does not apply. Likewise, there is no VREF (reference voltage) compared to the signal voltage. By eliminating the time necessary for the adjustment and retention of the time necessary to enable "the voltage ranges to detect around VREF", the operating frequency is considerably increased with the lower energy consumption. In addition, all receivers 405 are self-timed, without the need for a global clock, allowing receivers 405 to be adjusted individually by eliminating the transmission deviation of the board or package level. Figures 8A and 8B are schematic diagrams illustrating the circuit detail comparators 435, according to Figure 4. Each comparator 435 7 includes a differential amplifier 802 (Figure 8A) or 852 (Figure 8B), which is similar to the differential amplifier. 702 of Figure 7A and the multiple inverters 804 (Figure 8A) u 854 (Figure 8B) in series. The full rail output signals of comparators 802 and 852 (VTl, VT2, VT3, / VTl, / VT2 and / VT3) are transmitted to all "XOR" 425 single-ended receivers (Figure 4). The selection of VT1, VT2 or VT3 is determined based on the test for the signal rate substantially equal to that of the generation path of the output signal SN of the receiver 405. Figure ~ 9 is a schematic diagram illustrating the 405 receivers with individually adjustable delays, to eliminate deflection during transmission and convert small oscillation to large oscillation by comparators 410. To tune the operating frequency or voltage oscillation for optimal performance, each 405 receiver has a recorder 05 to store data and enable the delivery of one of the three VTl and / VTl, VT2 and / VT2 or VT3 and / VT3 to the XOR 425 (Figure 4).

Figure 11 is a perspective view of the permanent wiring arrangement of a co-ordinated master 1100 for bidirectional signal communication. Master 1100 includes receivers 405 and return transmitters 1105 coupled together. More particularly, each received single end signal, such as the signal SO, is coupled to a corresponding receiver 4Q5, such as the SO receiver, and to a corresponding transmitter 1105, such as »1 transmitter T0. Preferably, all single-ended signals SNx can be grouped together with a single pair of SSVTR and / SSVTR references. However, the person skilled in the art will recognize that for a given operating frequency, the load of SSVTR and / SSVTR and the unbalance of signals reduces the number of SNx signals that can be grouped together, as shown in the Figure. 11, the arrangement is made so that the capacitances, resistors and inductances in SSVTR, / SSVTR and all SNx single-ended signals are balanced. " Also, since SSVTR and / SSVTR go to all 405 receivers, the total load on SSVTR and / SSVTR needs to be reduced to a minimum.

Using devices with very low energy dissipation and close to the physical package, the collector can be made as ortho-orthopedic as possible, which, in turn, allows for short propagation times and high data rates ^ As shown in Figure 2B , the controlled impedance transmission lines, terminated in resistor, can operate at 1 GHz signal rates (1 ns cycle). The characteristics of transmission lines are strongly affected by the load caused by integrated circuits such as DRAM, mounted on the collector. These integrated circuits add capacitance to the lines, which both decrease the impedance of the lines and decrease the transmission speed. In the charged environment, the impedance of the collector is probably of the order of 25 ohms and the propagation speed is 7.5 cm / ns. Care must be taken not to drive the collector of the two devices at the same time. Thus for collectors smaller than about 12 cm, an inactive cycle (for example 2 ns) is necessary to set the collector to change from one impeller to another impeller. For older collectors, more than one cycle may be necessary for "the signals to be established before a new transmitter can boost the signal." Unlike the RAMBUS technology, the collector length does not reduce the frequency of operation in the discontinuous mode. Same device Figure 12A is a block diagram in perspective view, illustrating a point-to-point system 1200, which includes a bi-directional master 1205, coupled via transmission lines 1215 to a slave device 1210 Bi-Directional Transmission lines 1215 include upper SNx 1220 signal lines, SNx 1225 lower signal lines and 1230 S-SVTG lines, and / SSVTR As illustrated in Figure 12B, a block diagram in perspective view , which illustrates a 1200 point-to-point system, incorporating terminal resistors 1235, which internally use gate-to-ground F-channel devices, eliminating the need for space to connect r external resistances and reduces the cost. It will be appreciated that terminating resistors 1235 can be realized using internal resistors instead of gate-to-ground P-channel devices. The termination of both ends _with the appropriate characteristic impedance ~ is preferred for bidirectional signals on a manifold. Since "intra-chip" blocks are physically close, the impedance matching resistors are not necessary: Small pull-up devices are sufficient. Similarly, when the inter-chip connections are physically close, the impedance matching resistors can be replaced with small upward traction devices to reduce the cost and energy and maintain the same rate of deviation.

It will be appreciated that multiple collectors are required for devices such as SLDRAM, DDR, SDRAM or DDR SRAMs, where signals are transmitted and received simul- taneously. Figure 13A is a block diagram in perspective view, illustrating a combined unidirectional and bidirectional 1300 system for SLDRAM _in a single integrated circuit. "" The 1300 system includes a 1305 master (for example a memory controller) coupled by means of transmission lines 1315 to slave devices 1310 (for example, SLDRAMs). Master 1305 transmits direction and control signals by address and control lines, 1320 and 1325, transmits / receives data signals through data lines, 1330 and 1335, transmits over lines 1340 SSVTR and / SSVTR, a first set of references of SSVTR and / SSVTR (ie SSVTRO and / SSVTRO) to examine the direction and control signals, and "transmits a second set of references of SSVTR and / SSVTR (ie, SSVTR1 and / SSVTR1 ) to the slave devices 1310. The address and control portion of the system 1300 handles unidirectional signals needed only by the slave devices 1310. The data portion of the system 1300 is bidirectional based on whether the specified control signal is an operation READING OR WRITING For a SLDRAM, the 40-bit command and address is sent in a packet of four words "of 10 bits, SSVTRO and / SSVTRO, which can be referred to as the differential clock of the system, which and operates at 500 MHz. A Phase Locked Loop (not shown) is used to lock the clock frequency and time for various internal purposes and drives the data output with SSVTR1 and / SSVTR1 on both edges for a data rate 1 GHz. All high frequency signals are terminated at both ends of the collector with their characteristic impedance. The termination at the end of the memory controller may include external resistances, internal resistances or internal P-channel gate-to-ground devices, since this memory controller is usually the master device and is fixed. Since the number of components (SLDRAMs) 1310 (which operate as _ slave_ devices) is variable, the components 1310 are preferably terminated by external resistors at the end of the transmission lines. The 18-bit bidirectional data collector 133 Q and 1335 operates at the same frequency as the system clock for synchronization and sends data in eight 18-bit words in four clock cycles (8 ns) or 2-25 gigabytes / sec from a single SLDRAM._ Care must be taken in balancing the load in SSVTRO and / SSVTRO by adding gates and inactive lines to observe in a manner comparable to SSVTR1 and / SSVTR1. This load balance makes the deviation regime because the load will be similar and allow similar margins for all signals. When greater bandwidth is required, a 1350 system can be used for collectors, as shown in Figure 14B. Two separate channels of SLDRAMs * 1310 are used with a single memory controller 1305. This configuration allows a peak data bandwidth of 4.5 gigabytes / sec. Although the 1350 system does not require synchronous clocks for the 1305 transmitter or the 1310 receiver, the 1350 system can use synchronous clocks to transmit data at a particular time and frequency, for ease of testing and usability with the existing protocols of the synchronous DRAMs and SRAMs. . It may be convenient to use a slow clock chip or an internal ring oscillator to transmit data at high frequency without a high-speed clock for synchronization and to reduce noise and system power. Those skilled in the art can, with the teachings of this invention, achieve systems of various sizes, synchronous or asynchronous, of wide bandwidth. Five concepts, which further explain the systems of input and output circuits 210 of Figure 4, are provided below. "" " The first concept refers to having complementary references. As shown in Figure 14A, the prior art systems use a fixed voltage reference "VREF", whose value is around the midpoint of the high voltage logic level CVOH) and low logic level (VOL). The VREF generator (not shown!) Usually has some displacement of DC from the variation in the power supply used for its generation, this variation is illustrated as "VREFH" and "VREFL." It also has alternating current noise - (AC ) to instantaneous variations in the power supply voltage, ground rebound, capacitive coupling and inductive coupling with adjacent signals.The differential oscillation to the comparator used in the receiver in the prior art is illustrated by the arrows. the worst case of the difference signal in the prior art will be of the order of 1/3 to 1/4 of the oscillation of the total voltage of the signal.As shown in Figure 14B, the systems and methods of the invention use complementary references of SSVTR and / SSVTR, which have the same voltage oscillation as any signal (eg data or control) .In a preferred embodiment, this voltage oscillation is 500 mv with a logical high voltage (VOH) of 1.8- V and a logical low level (VOL) of 1.3 V. It will be appreciated that the average of the complementary reference voltages is around the midpoint of VOH and VOL at each instant of the tempo during the operation of this signaling system. Complementary signals and references have the same moments of transition and voltage oscillations, and are initiated at the same time from the same source (same device for inter-chips or general location for the intra-chip) to be sent to the receiver . In other words, the complementary references are observed just like any other signal. However, complementary references tilt every time other signals need to be transmitted. Since the complementary references use the power supply and ground at the same time, all noise is common. Therefore, the VREF (VREFH and VREFL) variations of the signal oscillation required in the prior art are not necessary in the systems and methods of the present invention. Due to the binary nature of the., Digital signaling, a complementary reference will always have opposite polarity to the signal at the start of the reference transition and at the end of the reference transition. Thus, a present reference will have a total oscillation of around 500 mv presented at some point, thus enabling the comparator to detect the signal voltage more easily than the prior art system, which has only 1/3 to 1/4 of the total signal oscillation. The reference and signal transition time may be half the transition time required by the prior art to achieve the same differential signal during the signal change. Those skilled in the art will recognize that, for optimum performance, VOH and VOL must be adjusted between a few hundred millivolts below the power supply and a few hundred millivolts above ground, with a difference of 500 millivolts between them. The difference can also be reduced to 200 mV up to 300 mV, if the inequalities of the device are reduced and the signals have little or no reflections, especially in the communication intr -microcircuits. The second concept refers to having double comparators for each incoming signal. Referring again to Figure 4, since the signal is compared to both complementary references, each receiver 10 has two comparators. One compares the signal SNx to SSVTR "and the other compares the signal SNx to / SSVTR.In the beginning of the discontinuous transition, the comparator- with a complete differential signal" on its input is coupled to the output of receiver 210 and the other comparator, which has no differential signal, is decoupled from the output of the receiver 210. This is done by initialization. If the SNx signal and the reference transition coupled, after the comparator quickly detects the signal as a life-amplifier, it rapidly amplifies the signal and drives the output to the opposite state. If the SNx signal does not transition (ie, only the reference transition), then the differential input to the comparator, which is coupled at the beginning of the reference transition, will be stably reduced through the transition time, finally up that a differential input is not supplied. This differential input to the comparator, which is decoupled at the beginning of the reference transition, will increase steadily through the transition time, finally until a complete differential signal is supplied. The comparator, originally coupled, without differential signal at the end of the transition, is decoupled and the comparator originally decoupled with the full differential signal at the end of the transition is coupled. The present invention uses two comparators to detect * a signal. In addition, the binary nature of the digital signals ensures a complete signal oscillation in one of the comparators at the start of each possible valid transition.

The third concept refers to initialization. Since only one comparator at a time is coupled to the output of the receiver, it is important for the proper operation to have the comparator with a full differential input signal coupled to the output "of the receiver 210 at the start of a burst. both / "all" signals SOx to SNx are initialized to the logical high level, VOH, Turning off all the impellers, which initialize the SSVTR to VOL, initialize the / SSVTR to VOH and connect the signals to the terminating resistors or activate the channel p with its active gates and the source connected to VTT (VTT is 1.8 V), the power consumption is reduced.The outputs of the receiver 210 for SO up to SN are preloaded to VCC using the device 1615 of the channel p "of the figure Amplify a small voltage difference to a large voltage difference. The voltage gain is typically 3 to 5 times based on the size of the device and the transistor _del_ correspondence. The inverter, placed after the differential amplifier *, provides an additional gain, in achieving almost complete oscillation based on the selection of the device size. The speed of the differential amplifier and the inverter achieves complete oscillation and depends on the differential signal available at its input. As shown in Figure 15A, a differential amplifier (and an inverter) can amplify a transition in both SNx and SSVTR 1500 very quickly. However, when SNx does not transition, the signal of the differential amplifier is reduced "" to adjust the noise and speed much lower (based on the inequalities and noise). The transition signal SN '(the differential amplifier and inverter saliaa) is shown i Orno a dotted line 1503. The region 1502 * "on the left side of line 1505, which defines the location where the XOR gate is slicing the interval , is labeled "Change." The region to the right of line 1505 is labeled "No Change." As noted above, when the signal does not transition, amplifier 1501 is reduced to adjust the noise, which is indicated as an indeterminate region 1506. The period of time before the amplifier reaches the indeterminate region 1506 is indicated as the time interval region 1504. This invention takes advantage of the time interval, enabling the address logic, described below, to pass The signal that changes to the output of the receiver and to prevent the indeterminate signal from passing By choosing appropriate device sizes and transition times, the time interval can be made. to operate the address logic, so that a "signal change" happens, but the "change of no signal" and the resulting undetermined voltage signal does not pass. It will be appreciated that some undetermined voltage level can pass as long as it is less than the logical threshold of the XOR gate that follows it and the other comparator can quickly restore the voltage level. It will further be appreciated that the time interval is dependent on the signal oscillation, the transition time of the reference signal, the process inequality and the signal reflection, etc. The fifth concept refers to the logic of direction. Referring to Figure 15B, the address logic circuit 1550 couples the appropriate comparator 155 to the receiver output 1560, and is based on the time generated by the differential amplifier, which uses SSVTR and / SSVTR and the present receiver output 1553. The address logic 1550 uses the SSVTR and / SSVTR and the present output signal from the receiver 1663. Referring to Figure 4, the initialization input signals SOx up to SNx to VOH, the reference / SSVTR to VOH , the reference -SSVTR to VOL, and the output signals of the receiver SO to SN "to VCC, couple the appropriate comparators 410 to the output 420 of the receiver, before the start of the burst. For the transition signal, the address logic 1550 changes, since this address logic XOR 1565 selects the appropriate amplified reference and the receiver output of the signal. Since both the amplified SSVTR reference and SNx tuning and the delay paths for the amplified SSVTR reference and for SNx to XOR 1565 are identical, the XOR 1565 does not change. Alternatively, if the input signal does not transition, the forward comparator 1555, which is coupled, is decoupled and the other comparator 155, which is not coupled, is now coupled. The output of the receiver signal does not change, and is actively driven by the coupled comparator 155 to restore the output level if required. The address logic 1550 is designed to occur during the time interval 1504, between the signal change 1502 and the non-signal change 1506, as explained above. The directional logic is done using an individual O-exclusive locally for each comparator for higher speed, better adjustment of the slicing time, and to improve the margins or adjust the deviations and inequalities. It will also be possible to have all the comparators decoupled from their receiver outputs, using the time of SSVTR and / SSVTR and a control signal for all the signal receivers of a collector channel to occur at the slicing time during the time interval , to reduce the number of devices in the receivers. This will reduce the operating bandwidth, since -1 appropriate comparator has to be "connected to the receiver's output, before starting the next transition." When all these elements are combined together, the total signaling system works with all the SOx signals up to SNx and / SSVTR starting at VOH, all the receiver outputs of signals previously loaded to VCC and SSVTR starting at VOL Before initiating the signal burst with the transition of complementary reference signals, all comparators with the Differential signal in them (SNx and SSVTR) are coupled to the receiver's outputs.For the signal transition, the address logic allows the signals to drive the output to the opposite voltage rail.For signals without transition, the address logic decouples the signals of the present comparator to the other comparator, to retain and / or restore the output of the receiver. continue with the overlap of the transitions with the direction logic until the delay of the address logic limits the bandwidth or the interval of time to allow the next transition. - "_ As shown in Figure 16, the single-ended signal receiver has gate differential amplifiers with a power-off signal or enables the receiver to disconnect the power to the receiver when it is not in use. to Figure 7A, inverters have been replaced by 1610 NAND gates (NO-Y) coupled to the power-off signal or enabling the receiver.In addition, a pulse transistor 1615 has coupled to node 708 in a discharge, to VCC at its source, and to the signal of power off or that enables the receiver, in its gate, to precharge SN to VCC The gate NAND 1615 afterwards - of the differential amplifiers also achieves the correct polarity in SN to start the cycle The desired initial condition is to preset high SNx, with SNx carried high by the terminating resistor or impulse device in the signal line and low SSVTR and / SSVTR high. The receiver has already been described. The device of the channel P in the common node of the output of the transmission gates is to preload the node 708 high quickly, its necessary, during the ignition or when the O-exclusive outputs have not reached stable levels. Using devices with very low energy dissipation and narrow physical packing, the collector can be made as short as possible, which, in turn, allows for short propagation times and high data rates. The completed controlled impedance transmission lines, as shown in Figure 12, can operate in signal regimes of 1 GHz (1 ns) or greater. The characteristics of the transmission lines are strongly affected by the load caused by the integrated circuits, such as the RAM assembled in the collector, ready integrated circuits add grouped capacitance to all the lines, which decreases the impedance of the lines and lowers the speed of transmission. In the charged environment, the impedance of the collector will probably be of the order of 25 ohms and the propagation speed of 7.5 cm / ns. In an application that requires a fast read-to-write collector or vice versa, as shown in Figure 17, the signal-transition time is chosen to be around 25 to 30% of the signal rate (half the time of the Cycle 5. The amplification starts in the next 25 to 30% of the signal signal regime.The impeller is turned off to set the signals down in about the next 25 to 30% of the signal "rate." It will be appreciated that the next cycle, where It inverts the signal or data direction, it can be done without loss of efficiency of the collector, where the devices are close to each other and the settling time of the collector is less than half of the signal regime. point-to-point, incorporating gate-to-ground P-channel devices that use internally terminating resistance, high-end point-to-point systems can be built, as shown Figure 13B. The terminating resistors, incorporated internally, eliminate the need for space to connect to external resistors and reduce the cost. It is also possible to switch the P-channel devices on the side of the transmitter to reduce the current - required in the discharge of the signal lines to the desired voltage. Both the CPU and the memory controller have devices that terminate in the P-channel, whose sizes can be chosen to equal the characteristic impedance of the line, when its gates are at the potential to ground. The gates of the P-channel devices use a signal that is a complement to the receiver 7 by enabling and disabling the receiver end and the transmission end. This change can be made while the receiver is in high mode, and before starting the burst on the signal lines. The internal resistance can also be used in place of the P-channel devices to ground. Using multiple collectors as described in the next section, a CPU to the collector width of the memory controller can be reduced to 32 (36) "from 64 (72) or the bandwidth can be increased considerably. fast) of the rear side of the CPUs can also be accelerated, the number of pins in the CPU can be reduced and the PBSRAMs can be changed from X36 to X18, thus reducing the size of the die and the cost. Figure 19 shows a 1900 system that has multiple collectors for devices such as the SLDRAM, DDR SDRAM or DDR SRAMs, where the signals are received simultaneously. The collector 1920 of the system clock starts from a clock source 1915 at the opposite end of the memory controller 1905, is connected to all the devices 1910, whose data outputs are connected to the collector 1920 and terminate in the 1905 controller "of memory The load on the clock signal corresponds to the load of the data output and the references of -SSVTR and / SSVTR.It will be appreciated that the clock can depend differentially (preferably) or single end, in the frequency requirements and the clock system. The oscillation of the clock voltage can be similar to SSVTR and / SSVTR to have a similar receiver. To have the same delay, the length of traces of the collector 1920 of the clock corresponds to the length of traces of the references SSVTR1 and / SSVTRl. The 1915 source of the clock introduces SSVTR1 ~~ / SSVTR1 and the data from DDRDRAM at different times, depending on its location on the collector 1920. so the "data, SSVTR and / SSVTR arrive at the 1905 contributor at about the same time, Regardless of which DDRDRAM is driving the data, each DDRDRAM can optionally use a DLL (delay lock loop) to reduce the 1915 clock to delay the data, if necessary for synchronization in the 1905 controller. To reduce an additional pin - the timed system, where-the data transmission is "predictable, a DLL can be used to generate / SSVTR1, which has the same time and voltage characteristic, but opposite polarity, at the end of the receiver. The DLL will play the clock on all components (which include the 1905 driver and the DDRDRAM 1910). The driver is aware of the cycle in which the data and SSVTR1 reference is predicted will arrive. After starting the nn-cycle of writing by the direction and command signals, the DDRDRAM will know the cycle in which the input data will arrive. The DLL guides the signal / SSVTR1 only when the signal is needed by a particular component. The direction and command lines can be grouped with SSVTRO and / SSVTRO. The address and control collector unidirectionally carries input signals from the 1905 memory controller to the DDRDRAM 1910. The 10-bit command and address is sent in a 2-bit command and an 8-bit address. This 2-bit command is obtained by using / CE and / RAS in a signal on both edges of SSVTRO and / SSVTRO or the other signal for / CAS and / WE. The 8-bit address on two edges gives up to 16 bits of row address, which occurs with / CE and / RAS or up to 1 £ column bits and block address, which occurs with / CE and / CAS for the read cycle . The write cycle is done with 16 column bits and block address with / CE and / CAS and / WE. SSVTRO and / SSVTRO can be derived from the system clock (differential) and operating at the same or a multiple of the clock frequency of the system. As explained before_, a DLL can be used to lock the clock frequency in the memory controller 1905 for various internal purposes, to drive command and address signals, during read requests, and to push data in, SSVTR1 and / SSVTR1 for write requests. Using different references for the incoming data (SSVTR1 and / SSVTR1) and for the address and control (SSVTRO and / SSVTRO) further distinguishes the present invention from RAMBUS signaling. In RAMBUS, all the signals that come within the RDRAM are detected based on a single clock, while in the present invention, the contiol signals and direction signals are in different channels than the data signals. This enables operating the control and direction channel at different frequencies than the data channel. All anidirctional high-frequency signals (direction and control signals) end with their characteristic impedance at the collector end away from the 1905 controller. Since the 1905 controller is usually the master device and is usually fixed, all bidirectional signals (data signals) terminate at the end of the controller with an external or internal resistor or with an "internal gate-to-ground P-channel device." It will be appreciated that, to reduce the power, the termination P-channel device may be disconnected during the data write cycle The termination on the controller side is optional and may be a high resistance of about 10x the characteristic impedance, since the number of memory components, ie the auxiliary or slave devices, is variable, the memory components are preferably terminated by an external resistor at the end of the transmission line. The 18-bit bidirectional data collector operates preferably on the same frequency as the system clock for synchronization and preferably sends data from the single DDRDRAM, in four 18-bit words in 2 clock cycles (4 ns) or 2.25 gigabytes / sec Care is taken in the balance of the load in the SSVTRO and / SSVTRO adding gates and inactive lines to obtain results comparable to SSVTR1 and / SSVTRl. This load balancing makes similar deviation regimes and allows similar margins for all signals. When a larger bandwidth is required, three collectors can be used, as shown in Figure 20. Two separate DDRDRAM channels are used with a single memory controller. This configuration allows a peak data bandwidth of 4.5 gigabytes / sec. The direction and command signals can be shared between the two channels in the SSVTRO ^ and / SSVTRO.The clock and data are divided to "have" 36-bit data collectors, using SSVTR1, / SSVTR1, SSVTR2 and / SSVTR2 This saves pins compared to the antennal technique of the RDRAM double channel Although the invention does not require a synchronous clock for the transmitter or receiver, it can use a synchronous clock to transmit data at a particular time and frequency for ease of testing. and utility with existing DRAM and SRAM synchronization protocols.It may be convenient to use a multiplier of "slow clock chips or an internal ring oscillator to transmit data at high frequency, without a high-speed clock for synchronization to reduce the noise and the energy of the system. Those skilled in the art can construct various high bandwidth systems, synchronous or asynchronous, of various sizes, in accordance with the present teachings. The above description of the preferred embodiments of the present invention has been presented only in "example form, and other variations and modifications of the modalities and methods, described above, are possible in the light of the foregoing teachings. For example, although the system and the method have been described "as the transmission of the SSVTR and / SSVTR signals from a master device 205 ^ a receiver 405, a person skilled in the art will recognize that a reference can be sent and the complement is generated. on the side of receiver 405. Using the technique with other technologies, such as bipolar or gallium arsenide, which have similar switching devices and gates, can be "used alternately. The components of this invention can be carried out using a digital computer programmed for general purposes, using application-specific integrated circuits, or using a network of conventional interconnected components and circuits. The modalities described here are not intended to be exhaustive or restrictive. The present invention is limited only by the following claims.

Claims (106)

CLAIMS ^

1. A method for detecting a transition in a signal entering from a prior known logic state, this method comprises: - - - obtaining an oscillation reference; receive an input signal; and - "" comparing the oscillation reference against the input signal, for < detect a transition in the input signal in relation to the known previous logical state.

2. The method of claim 1, wherein the comparison includes generating a first result; and further comprises generating a "control signal, based on the previous logical state, to control whether the first result propels an output signal.

3. The method of claim 2, wherein the generation of the control signal includes comparing the oscillation reference and the output signal.

4. The method of claim 3, wherein the first result propels the output signal from the previous logical state to the first result; and the generation of a control signal includes comparing the oscillation reference and the output signal, while this output signal is still "logically equal to the previous logical state.

5. The method of claim 3, wherein the first result propels the output signal from the previous logical state, towards this first result; and the generation of a control signal includes comparing the oscillation reference and the output signal, after which this output signal logically equals the first result.

6. The method of claim 1, wherein the oscillation reference is synchronous with the input signal.

7. The method of claim 1, wherein the oscillation reference provides voltage and timing attributes.

8. The method of claim 1, wherein the oscillation reference is denied. - - _ ^ =

9. The method of claim 11 further comprising: obtaining a complement of the oscillation reference; and comparing the complement against the current signal that enters and against the previous logical state, in order to detect a transition in the incoming signal in relation to the previous logical state.

10. The method of claim 1, wherein the oscillation reference includes a synchronous source of oscillation source and time reference, having a deviated rate and a cycle time, this deviated rate is substantially equal to half the time of cycle.

11. A system for detecting a transition in an incoming signal, from a "prior" logical state, "* this system" comprises: - - a first and second input terminals, to receive, respectively, an oscillation reference and a signal of entry; an output terminal, which supplies an output signal, logically equal to the previous logical state, - a first comparator, coupled to the first and second input terminals, for comparing the reference and the input signal, to generate a first result; and _ a first controller, coupled to the first comparator, for coupling the first result to the output terminal, based on the previous logical state. "

12. The system of claim 11, wherein the first controller compares the oscillation reference and the output signal.

13. The system of claim 12, wherein the first result is coupled to the output terminal, for propelling the output signal from the previous logical state to the first result; and the first controller is coupled to compare the oscillation reference and the "output" signal, while this output signal is still logically equal to the previous logic state.

14. The system of claim 12, wherein the first result is coupled to the output terminal, for propelling the output signal from the previous logical state to the first result; and Z the first controller is coupled to compare the oscillation reference with the output signal, after which this output signal logically matches the first result.

15. The system of claim 11, wherein the oscillation reference is synchronous with the input signal.

16. The system of claim 11, wherein the oscillation reference provides voltage and synchronization attributes.

17. The system of claim 11, wherein the oscillation reference is denied. -

18. The system of claim 11, wherein the oscillation reference includes a synchronous source of oscillation source and time reference, having a deviation rate and a cycle time, this deviation rate is substantially equal to half the time Cycle.

19. The system of claim 11, further comprising a third input terminal, for receiving a complement of the oscillation reference; a second comparator, coupled to the second and third input terminals, for comparing the complement and the input signal, to generate a second result; and ~ a second controller, coupled to the second comparator, for coupling this second comparator to the output terminal, based on the previous logical state.

20. A system for detecting a transition in an input signal from a previous logic state, "this system comprises: an output terminal, which supplies an output signal logically equal to the previous logic state, a first amplifier, to amplify the difference between the input signal and an oscillation reference, to generate a first result, - a second amplifier, to amplify the difference between the input signal and a complement of the oscillation reference, to thereby generate a second result; a first switch, coupled to the first amplifier, for coupling the first result to the output terminal, based on first criteria; a second switch, coupled to the second amplifier, for coupling the second result to the output terminal, based on second criteria; a first controller, to control the first criteria, based on a comparison of the oscillation reference and the output signal; and a second controller, to control the "second criteria, based on a comparison of the complement and the output signal.

21. The system of claim 207, wherein the first switch couples the first amplifier to the output terminal, for propelling this output signal from the previous logic state to the first result; the input signal is opposite - logically to the previous logic state, - the first controller is coupled to compare the oscillation reference and the output signal, "while the output signal is still logically equal to the" previous logic state; and the second controller is coupled to compare the complement with the output signal, while this output signal is still, logically, the same as the previous logic state.

22. The system of claim 20, wherein the first switch couples the first amplifier to the output terminal, for propelling the output signal from the previous logic state, to the first result; "the input signal is logically equal to the previous logical state, the first controller is coupled to compare the oscillation reference and the output signal, after which the output signal logically equals the first result; And the second controller is coupled to compare the complement and the output signal, after which this output signal logically matches the first result.

23. The system of claim 20, wherein the reference is synchronous with the input signal.

24. The system of claim 20, wherein said reference provides voltage and synchronization attributes. - ^ -

25. The system of claim 20, wherein the reference is denied.

26. The system of claim 20, wherein the reference includes a synchronous oscillation source voltage and time reference, having a deviation rate and a cycle time, this deviation rate is substantially equal to half the cycle time .

27. A communication system ", which comprises: a transmitter, to transmit a first oscillation reference, a second reference, which is complementary to the first oscillation reference, and a new signal, to a receiver; "" transmission lines, coupled to the transmitter, to bring the first oscillation reference, the second oscillation reference and the new signal to the receiver; and a receiver, coupled to the transmission lines, to receive the first oscillation reference, the second oscillation reference and the new signal, and to detect a transition in the new signal, from a known prior logic state of the new signal, based on a comparison of the new signal and one of the oscillation references.

28. The system of claim 27, wherein the receiver includes: a first, second and third input terminals, for receiving, respectively, the first reference of oscillation, the second reference of oscillation and the new signal; an output terminal, which supplies an output signal, this output signal has a quality signal state, logically equal to the previously known logic state; a first comparator, coupled to the first and third input terminals, for comparing the first oscillation reference and the new signal, to generate a first result; and a controller, coupled to the first comparator and the second comparator, for coupling one of the first result or the second result to the output terminal, based on whether there is a transition in the new signal.

29. The system of claim 28, wherein the controller compares the values based on the oscillation references and the output signal.

30. The system of claim 29, wherein: the first result is coupled to the output terminal, for propelling the output signal from the previous logical state to the first result; and the controller is coupled to compare values based on the oscillation references and the output signal, while this output signal is still logically equal to the previous logic state. -

31. The system of claim 29, wherein: the first result is coupled to the output terminal, for propelling the output signal from the previous logical state to the first result; and the controller is coupled to compare values based on the oscillation references and the output signal, after which this output signal logically matches the first result. ""

32. The system of claim 28, wherein the input signal is double ended.

33. The system of claim 28, wherein the oscillation references are synchronous with the new signal.

34. The system of claim 28, wherein the oscillation references provide voltage and synchronism attributes.

35. The system of claim 28, wherein the first oscillation reference is denied. _

36. The system of claim 28, wherein the first reference "of oscillation includes * a synchronous source of oscillation source and time reference, which has a rate of deviation and a cycle time, this rate of deviation is substantially equal to the time Cycle.

37. The system of claim 26, wherein the transmitter includes a memory controller; and the receiver includes a memory.

38. The system of claim 26, wherein the transmitter includes a microprocessor; and the receiver includes a system controller.

39. The system of claim 38, wherein the system controller includes a memory controller.

40. A signal receiving system, to detect a transition in. a signal that enters, from a previous logical state, this system comprises: (a) an output terminal, which supplies an output signal logically equal to the previous logical state, - (b) a first receiver, which includes: (i) a first comparator, for comparing an oscillation reference against the input signal, to generate a first result; (ii) a first switch, coupled to the first comparator, for coupling the first result to the output terminal; and (iii) a first controller, coupled to the first switch, for comparing the oscillation reference against the output signal, for generating a control signal, for controlling the first switch ^ and (c) a second receiver, in parallel to the first receiver, this second receiver includes: (i) a second comparator, APRA comparing an oscillation reference complement against the input signal, to generate a second result; (ii) a second switch, coupled to; - second comparator, for coupling the second result to the output terminal; and "" (iii) a second controller, coupled to the second switch, to compare the oscillation reference complement against the output signal, to generate a control signal, to control! the second switch.

41. The system of claim 40, wherein: the first result is coupled to the output terminal, to propel the output signal from the previous logical state to the first result; the first controller is coupled to compare the oscillation reference and the "output" signal, while this output signal is still logically equal to the previous logical state, and the second controller is coupled to compare the complement and the output signal, while this output signal is still logically equal to the previous logical state.

42. The system of claim 40, wherein the first result is coupled to the output terminal, for propelling the output signal from the previous logical state to the first result; the first controller is coupled to compare the oscillation reference and the output signal, after which this output signal logically equals the first result; and the second controller is coupled to compare the complement and the output signal, after which this output signal logically matches the first result.

43. A transmission system, which comprises: a generator, for generating a synchronous source voltage of oscillation and time reference, having a deviation regime that is about half the cycle period of the oscillation reference; a transmitter, coupled to the generator, APRA transmit a signal and oscillation reference to the receiver.

44. A method for comparing an input signal to a previous logic state, comprising the steps of: obtaining an oscillation reference and a complement of the oscillation reference; receive the input signal; comparing, by a first comparator, the oscillation reference against the input signal, to generate a first result, - comparing, by a second comparator, the complement against the input signal, to generate a second result; "use a control signal, based on the previous logical state, to control whether the first result or the second result passes as an output signal.

45. The method of claim 44, wherein: the previous logical state propels the output signal by means of the first comparator; - the input signal is logically the same as the previous logical state; and _ the control signal allows the second result to pass as the output signal.

46. The method of claim 44, wherein: the previous logic state propels the output signal by means of the first comparator; "the input signal is logically opposite to the previous logical state, and the control signal allows the first result to pass as the output signal.

47. A method for transmitting and receiving a small-end signal of small oscillation, this method comprises: transmitting a simple, small-oscillation signal from a source to a receiver; transmitting from the source to the receiver a first oscillation reference, which has substantially the same deviation regime as the single-ended signal, when the single-ended signal is transitioned; transmitting from a source to the receiver a second oscillation reference, which is complementary to the first oscillation reference; receive the signal and oscillation references in the receiver; generate an output by comparing the signal and one of the oscillation references; coupling the output to an output terminal of the receiver, when the signal transitions; and uncoupling the output from the receiver's output terminal, when the signal does not transition.

48. The method of claim 47, wherein the source is coupled to the receiver, by means of a transmission line on a manifold, which is terminated at both ends by the characteristic impedance of the "transmission line.

49. The method of claim 47, wherein the source is coupled to the receiver by means of the "point-by-point connection, which is terminated on both ends

50. The method of claim 47, wherein the signal has a small oscillation, less than one volt.

51. The method of claim 47, wherein the signal has a small oscillation, less than 40% of the supply voltage.

52. The method of claim 47 *, wherein: the signal has a deflection rate of less than 110% of the signal rate, for signals transmitted above the 600 MHz rate.

53. The method of claim 47, wherein the oscillation references have substantially the same oscillation.

54. The method of claim 47, wherein the oscillation references have substantially the same load.

55. A method for transmitting and receiving a small-end, small-oscillation signal, this method comprises: transmitting a simple, small-oscillation signal from a source to a receiver, this receiver includes a first comparator, a second comparator and a exit terminal; "transmit from the source to the receiver, a pair of complementary oscillation references that have substantially the same deflection regime as the single-ended signal, when this simple-ended signal is transitioned; receive the signal and oscillation references in the receiver: - - - only connect one of the comparators to the output terminal, based on the current logic value at the output terminal and the value based on the oscillation references, and uncouple the other comparator.

56. The method of claim 55, wherein the coupling step includes coupling the single comparator to the output terminal, when the single-ended signal is transitioned.

57. The method of Claim 55, wherein the coupling step includes uncoupling the single comparator and coupling the other comparator, when the single-ended signal does not transition.

58. The method of claim 57, wherein the other comparator supplies an output signal, which restores the current logical value at the output terminal.

59. The method of claim 56, wherein the comparators compare the single-ended signal, with the oscillation references, to generate "output signals.

60. The method of claim 53, wherein the single comparator detects the single-ended signal in the differential mode with the same noise immunity as the differential signals, when the single-ended signal is transitioned.

61. The method of claim 59, wherein the other comparator detects the single-ended signal in the differential mode, with the same noise immunity as the differential signals, when the single-ended signal does not transition.

62. The method of claim 47, wherein the source is located in the first block of a device and the receiver is located in another block of the same device, with the active terminators of the intra-device p-channel.

63. A system, which comprises: a control manifold, having a master end and a secondary or slave end; a first reference manifold, having a master end and a slave end; a first reference transmitter, coupled to the master end of the first reference collector, for transmitting an oscillation reference there; a data collector, which has a master end and a slave end; a second reference collector, which has a master-end and a slave end; a second reference transmitter, coupled to the master end of the second reference collector, for transmitting an oscillation reference there; a third reference transmitter, coupled to the slave end of the second reference collector, for transmitting an oscillation reference there; a master device, coupled to the master end of the control manifold, for transmitting a control signal over the control manifold, coupled to the master end of the data collector, for transmitting a first data signal, associated with the control signal to the collector of data and to receive a second signal sensitive to the control signal from the data collector, and coupled to the master end of the second reference collector, to receive and use the oscillation reference from the third reference transmitter, to detect a transition in the second data signal, - and a slave device, coupled to the slave end of the collector of control, to receive "the control signal from the master device, coupled to the slave end of the first reference collector, to receive and use the oscillation reference from the first reference transmitter, to detect a transition in the control signal , coupled to the slave end of the data collector, to receive the first data signal, associated with the control signal, from the master device and to transmit the second data signal, responsive to the control signal, to the master and coupled device to the slave end of the second reference collector, to receive and use the oscillation reference from the second reference transmitter, to det ect a transition in the first data signal.

64. The system of claim 63, wherein the control manifold has a first load and the data collector has a second load.

65. The system of claim 64, wherein the first load is equal to the second load. _ _

66. The system of claim 64, wherein the first load is different from the second load.77

67. The system of claim 63, further comprising a second data collector, for carrying a third data signal, associated with the control signal.

68. The system of claim 63, wherein each of the control manifold, the first "" reference manifold, the data collector and the second reference manifold, has a terminating resistor internally at the master end and a terminating resistor externally at the slave end.

69. The system of claim 63, further comprising a second master device, coupled to the control manifold, for receiving a control signal from the master device, coupled to the first reference manifold, to receive the oscillation reference from the first transmitter of reference, coupled to the data collector, to receive a data signal from, and transmit a data signal to, the master device, and coupled to the -second reference collector, to "receive the oscillation reference from the second reference transmitter .

70. The system of claim 69, further comprising: a clock collector, which couples the first slave device to the second slave device in turn to the master device; and a clock source, for generating a clock signal in the clock collector, to enable substantially simultaneous reception of signals from the first and second slave devices in the master device.

71. A method that comprises; using a master device to transmit a control signal by means of a control manifold to a first slave device; transmitting a first oscillation reference to detect transitions in the control signal by means of a first reference collector to the first slave device; using the master device to transmit a first data signal associated with the control signal by means of a first data collector to the first slave device; and transmitting a second reference oscillation, to detect transitions in the first data signal, by means of a second reference collector to the first "slave device.

72. The method of claim 71, further comprising applying a first load to the control collection and applying a second load to the first data collector.

73. The method of claim 72, wherein the first load is equal to the second load. ~

74. The method of claim 72, wherein the first load is different from the second load.

75. The method of claim 71, further comprising using the master device APRA to transmit a second data signal, associated with the control signal, by means of a data collector, to the first slave device.

76. The method of claim 71, further comprising terminating nothing one of the control manifold, the first reference manifold, the first data collector_and the second reference manifold with a terminal resistor internally at one end and externally at the other end.

77. The method of claim 71, further comprising: supplying a first slave device between the master device and the first slave device; supplying a clock collector, coupled from the first slave device to the second slave device in turn to the master device; and generating a clock signal in the clock collector, to enable substantially simultaneous reception of signals in the master device from the first and second slave devices.

78. A method comprising: - receiving a control signal by means of a control manifold from a master device; receiving a first oscillation reference, to detect transitions in the control signal, by means of a first reference collector; receiving a first data signal, associated with the control signal, by means of a first data collector from the master device; and ~ ~ receiving a second oscillation reference, to detect transitions in the first data signal by means of a second reference collector. - - ~ r -

79. A method comprising: using a master device to transmit a control signal by means of a control manifold to a first slave device; transmitting a first oscillation reference to detect transitions in the control signal by means of a first reference collector to the first slave device; using a master device to receive a first data signal, responsive to the control signal by means of a first data collector from the first slave device; and using a master device to receive a second oscillation reference to ~ detect _transitions in the first data signal, by means of a second reference collector, from the first slave device.

80. The method of claim 79, further comprising applying a first load to the control manifold and applying a second load to the first data collector.

81. The method of claim 80, wherein the first load is equal to the second load.

82. The method of claim 80, wherein the first load is different from the second load.

83. The method of claim 79, further comprising receiving a second data signal responsive to the control signal, by means of a second data collector from the first slave device.

84. The method of claim 79, further comprising terminating each of the control manifold, the first reference manifold, the first data collector and the second reference manifold with a terminal resistor internally at one end and externally at the other end.

85. The method of claim 78, further comprising: - - supplying a second slave device, between the master device and the first slave device; supplying a clock collector, coupled from the first slave device to the second slave device, in turn to the master device; and generating a clock signal on the clock collector, to enable the substantially simultaneous reception of signals from the first and second slave devices to the master device.

86. A method comprising: receiving a control signal by means of a control manifold from a master device, receiving a first oscillation reference to detect transitions in the control signal by means of a first reference collector; a data signal, responsive to the control signal, by means of a manifold of Hatos to the master device, and transmitting a second reference of oscillation, to detect transitions in the data signal, by means of a second reference collector, to the master device.

87. A system, which comprises: a control manifold door; a first door of the reference manifold; a first reference transmitter, coupled to the first gate of the reference collector, for transmitting an oscillation reference; a first gate of the data collector; a second door of the reference manifold; a second reference transmitter, coupled to the second gate of the reference collector, for transmitting an oscillation reference; and a master device, coupled to the gate of the control manifold, for transmitting a control signal. the gate of the control manifold, coupled "to the first gate of the data collector, to transmit a first data signal, associated with the control signal to the first gate of the data collector", "and" "to receive a fingernail second data signal, responsive to the control signal from the first gate of the data collector, and coupled to the second gate of the reference collector, will receive and use an input oscillation reference from the second gate of the reference collector " , to "detect a transition in the second data signal.

88. The system of claim 87, wherein the gate of the control manifold has a first load and the data collector gate has a second load.

89. The system of claim 88, wherein the first load is equal to the second load.

90. The system of claim 88, wherein the first load is different from the second load.

91. The system of claim 87, further comprising a second data collector gate, coupled to the master device, in which this master device transmits a third data signal associated with the control signal to the second gate of the data collector and receives a fourth data signal, responsive to the control signal from the second gate of the data collector.

"92. The system of claim 87, wherein each of the gate of the control manifold, the first gate of the reference manifold, the gate of the data collector and the second gate of the reference manifold, have a terminal resistance. internal

93. The system of claim 87, further comprising a slave device, coupled to the gate of the control manifold, for receiving a control signal from the master device, coupled to the first door of the reference manifold, to receive the first reference of oscillation from the first reference transmitter, coupled to the first gate of the data collector, to receive a first data signal from, and transmit a second data signal to, the master device, and coupled to the second gate of the data collector. reference, "to receive the second reference of oscillation from the second reference transmitter.

94. The system of claim 93, further comprising a clock collector gate, for receiving a clock signal by means of this "clock collector" gate, from the slave device.

95. A system comprising: 1 a control manifold door, a first reference manifold door, "" a data collector gate, a second reference collector gate; ~~ a first reference transmitter, coupled to the second gate of the reference collector, to transmit an oscillation reference to the second gate of the reference collector, and a first slave device, coupled to the gate of the control manifold, to receive a control signal of the gate of the control manifold , coupled to the first gate of the reference collector, to receive and use an oscillation reference from the first gate of the reference collector, to detect a transition in the control signal, coupled to the gate of the data collector, to receive a first data signal, associated with the control signal, from the gate of the data collector and for transmitting a second data signal, responsive to the control signal, to the rta of the data collector, and icopiada to the second door of the reference collector, to receive and use the oscillation reference from the second door of the reference collector, "to detect a transition in the data signal. "

96. The system of claim 95, wherein the gate of the control manifold has a first load and the gate of the data collector has a second load.

97. The system of claim 96, wherein the first load is equal to the second load.

98. The system of claim 96, wherein the first load is different from the second load.

99. The system of claim 95, further comprising a second data collector gate, coupled to the first slave device, for receiving a third data signal, associated with the control signal and for transmitting a fourth data signal, responsive to the control signal. - -

100. The system of claim 95, wherein each of the gate of the control manifold, the first gate of the reference collector, the gate of the data collector and the second gate of the reference collector have an external terminating resistor.

101. The system "of claim 95, further comprising: a clock collector gate, and a clock source, for generating a clock signal from the gate of the clock collector to the master device.

102. A system, comprising: - - _ an element for transmitting a control signal by means of a control manifold to a first slave device; an element for transmitting a first oscillation reference, for detecting transitions in the control signal by means of a first reference collector to the first slave device; an element for transmitting a first data signal, associated with the control logic by means of a first data collector to the first slave device; and an element for transmitting a second oscillation reference, for detecting transitions in the first data signal by means of a second reference collector to the first slave device.

103. A system, comprising: an element for receiving a control signal by means of a control manifold, from a master device; an element for receiving a first oscillation reference, for detecting transitions in the control signal by means of a first reference collector; an element for receiving a first datum signal, associated with the control signal, by means of a "first data collector, from the master device, and an element for receiving a second oscillation reference, for detecting transitions on a first signal of data by means of a second reference collector.

104. A system, comprising: an element for transmitting a control signal by means of a control manifold to a first slave device; an element for transmitting a first oscillation reference, for detecting transitions in the control signal by means of a first reference collector to the first slave device; an element for receiving a first datum signal, responsive to the control signal, by means of a first data collector, from the first "slave device", and an element for receiving a second oscillation reference, for detecting transitions in the first data signal, by means of a second reference collector, from the first slave device.

105. A system, which comprises: an element for receiving a control signal by means of a control manifold, from a * "master device; an element for receiving a first oscillation reference, for detecting transitions in the control signal, by means of a first reference collector; an element, for transmitting a data signal, responsive to the control signal, by means of a data collector, to the master device; and an element for transmitting a second oscillation reference, for detecting transitions in the data signal, by means of a second reference collector, to the master device.

106. The method of claim 47, wherein the source includes a block of a device and the receiver includes another block of the same device, with active terminators of channel p, intra-devices. - SUMMARY OF THE INVENTION A system of the present invention uses small time and voltage reference signals (SSVTR and / SSVTR) synchronous of differential source of variation, to compare single terminated signals of the same rotation index generated at the same time from the same circuit integrated for high frequency signaling. The SSVTR and / SSVTR signals keep the valid signals driven by the integrated transmission circuit all the time. Each signal receiver includes two comparators, one to compare the signal against the SSVTR and the other to compare the signal against the SSVTR. A present binary signal value determines which comparator is coupled to the receiver output, by optionally using the XOR logic with the SSVTR and / SSVTR. The comparator coupled in the receiver detects whether or not a change in the binary value of the signal occurred until the SSVTR and / SSVTR have changed their binary value. The same comparator is coupled if the signal transition occurs. If the transition does not occur, the comparator is decoupled. The system can use a first set of oscillating references in a first collector to detect transitions in the control information, and a second set of oscillating references to detect transitions in the data information.