CZ20003371A3 - Method and system for high-speed signaling for connecting LVSI CMOS circuits by interface - Google Patents

Abstract

The method and system uses a small-scale differential source synchronous voltage and time reference signals (SSVTR a / SSVTR) to compare simple signals with the same at the same time from the same integrated circuit for high frequency signaling. SSVTR and / SSVTR signals are flipped each time they are valid signals controlled by the transmitting integrated circuit. Each signal receiver (210) includes two comparators (410a, 410b), one for comparing signals to SSVTR and the other to compare signal to / SSVTR. Binary value the signal present determines which comparator (410a, 410b) is connected to the receiver output, possibly using logic XOR with SSVTR and / SSVTR. Connected Comparator (410a410b) at the receiver detects whether a change in binary value has occurred or not until the SSVTR and / SSVTR have changed binary value. The same comparator (410a, 410b) is connected if the signal changes. The comparator (410a, 410b) is disconnected when there is no transformation. The system uses the first a set of oscillating reference signals on the first bus for detecting transformations in control information and a second set oscillating reference signals for detecting transformations in the data information.

Description

A method and system for high-speed signaling for connecting LVSI CMOS circuits to an interface

Technical field

The present invention relates generally to the communication of computer signals, in particular an integrated circuit interface and a method of high-speed, block-transmitted signaling of data, control and address signals between a plurality of integrated circuits on a bus or from one to another under reduced power consumption.

BACKGROUND OF THE INVENTION

Semiconductor integrated circuits used in digital computing and other digital applications often use a group of interconnected VLSI circuits (VLSI, i.e., Vera Large Scale Integration) to realize binary communication over single or multi-segment transmission lines. Conventional transmission lines include tracks that are formed on a suitable substrate, such as a printed circuit board. For example, each transmission line may be constructed using so-called microstrip tracks from the tape tracks to form a transmission line having a characteristic impedance of the order of about 50 to 70 ohms. Each transmission line may optionally have its opposite ends terminated by their characteristic impedance. The output load on the control circuit for such a transmission line can be only about 25 to 35 ohms.

To consume a reasonable amount of current, high frequency signaling requires low amplitude signals. To allow the receiver to easily detect voltage oscillations (for example, from 0, 8 V to 4).

1.2 V) In a noise environment such as GTL, HSTL, SSTL or RAMBUS, the current must also be very large (for example of the order of 50 to 60 milliamps per control circuit). A typical receiver uses a comparator with a reference voltage signal (VREF) located midway between the input high voltage (VIH) and input low voltage (VIL). A VREF signal is a high impedance DC reference voltage that freely monitors the supply current over time, but cannot respond to instantaneous noise. High output voltage (VOH) and low output voltage (VOL) conventionally refer to signals output from a transmitting source, and VIL and VIH refer to signals coming at the input of the receiving device, even though they can be considered the same signal.

Giant. 1A is a block diagram illustrating a prior art receiver 10 using RAMBUS technology. The system 10 includes a solder pad (PAD) 100 connected by signal lines 103 to the internal input receivers 110. The VREF signal 105 is connected to each indoor receiver 110. The VREF is generated from the power supply. The DC power supply value usually changes by 5%. Giant. 1B is a timing diagram 125 showing an example of a waveform of a high reference voltage (VREFh) and a low reference voltage (VREF1). The values of VREFh and VREF1 generally depend on the fluctuation of the current supply used to generate the VREF signal. For reliable detection of signal polarity, a large voltage variation is required, ie the difference between the high voltage signal (VIH) and the low voltage signal (VIL) and the stable signal levels above and below the VREF signal. The voltage ripple of current so-called single signal technologies is conventionally around 0.8 V.

Giant. 1C is a block diagram schematically illustrating a prior art receiver 150 using RAMBUS technology. Receiver 150 samples the level of the input signal 167 and the VREF signal 154 until the signal reaches a stable level and at this point the shutter gates 160 and 165 are turned off. As soon as the shutter gates 160 and 165 are turned off, the gating gate 172 is activated to eliminate current intrusion. Giant. ID is a timing diagram 175 illustrating the operation of the receiver 150 in an example signal. Receiver 150 samples the input reference signal and the input signal until the signal reaches a stable level, e.g., low logic level (VIL), and while the input signal is stable, the receiver 150 senses the value of the input signal. As mentioned above, in order for signal detection to be reliable, the signal voltage amplitude must be fast enough to allow all receivers 150 to sample a stable signal with an appropriate margin for the set and hold time. This voltage amplitude should occur within less than 30% of the minimum cycle time to leave an edge for the timeshift, setup and signal hold times. As the minimum cycle time decreases to less than 1 nanosecond, the margins for time shift, adjustment, and hold time are reduced, with the additional current load in the control circuit being a high capacitive load from the high frequency environment. The low voltage differential signaling (LVDS) used in the IEEE P1596.3 can overcome these problems by using 250mV voltage amplitude at the expense of running complementary signals. Running complementary signals inevitably increase the number of pins and packet size.

In addition, computer systems typically employ a bus system in which several devices are connected to the bus. Most use clocks to check the validity of data, address, and control signals. Giant. 21 illustrates a prior art DRDRAM system 21Q2 that uses a clock line 2130 having two segments 2136 and 2138. One segment 2136 extends from one end of the data bus to a turning point 2137 near the other end of the bus. The second clock segment 2138 extends from the turning point 2137 back to the first end of the data bus. The signal bus 2120 transmits data, address, and control signals. This topology ensures that the signal sent on the bus 2120 always travels simultaneously and in the same direction as the clock 2132 used by the signal receiving device. This works well if the collection of all signals and clock pulses is almost identical and the clock 2132 is used to sample and receive the signal. However, sometimes the system might require twice as much data bandwidth, in which case this type of bus system requires doubling the number of signals even though the address and control signals are identical and could be shared.

Accordingly, there is a need for low power control circuits and reliable receivers for high frequency operation of a large number of simple signals in existing technology on low cost VLSI digital systems.

SUMMARY OF THE INVENTION

The system of the present invention uses low-voltage synchronous voltage and timing reference signals from a differential source (SSVTR and / SSVTR) to compare simple signals of the same amplitude generated from the same high-frequency integrated circuit. signalizaci. It will be considered an advantage that / is used to indicate a logical NO (NOT). All signals are terminated by their characteristic impedances at both ends of the transmission lines. SSVTR and / SSVTR switch each time valid signal is transmitted by the transmission IC. Each signal receiver includes two comparators, one for comparing the signal with the SSVTR and the other for comparing the signal with the / SSVTR. The binary signal present determines which comparator is connected, ·· * »·«

9 · 999 · 9 99 «or using EXCLUSIVE-OR logic with SSVTR and / SSVTR. Until the SSVTR and / SSVTR change their binary value, the connected comparator in the receiver detects whether there is a change in the binary value of the signal. Again, it will be appreciated that the SSVTR and / SSVTR change their binary value each time the signal can change its binary value. The SSVTR and / SSVTR are preferably synchronized with the signal.

The method of the invention comprises the steps of obtaining an oscillating source of synchronous voltage and time reference and its complementary signal (SSVTR and / SSVTR), and receiving an input single signal. The method compares the oscillating reference signal with the input signal / by the first comparator to produce the first result and compares the complementary signal with the input signal by the second comparator to produce the second result. The method then selects one of the first result or the second result as the output signal based on the previous signal. The step of selecting one of the results comprises comparing the output signal to a reference signal (SSVTR) and a complementary signal (/ SSVTR). The selection step further comprises manipulating the output signal from the previous signal to the first result or the second result according to the comparator currently connected. If the input signal changes, the selection step involves maintaining the same comparator connection. If the input signal remains the same, the selection step involves disconnecting the currently connected comparator and connecting the second comparator. The method then allows the circuit to stabilize.

Preferably, the system and method eliminate the need for a high impedance VREF signal to compare small-scale single signals. This reduces the need for three different voltage levels (output high level, output low level and VREF level) to two different voltage levels (output high level and output *

9 ··· low level). Elimination of VREF reduces the necessary voltage oscillation and consequently reduces the power consumption. Using a dual comparator receiver allows the receiver to be connected to the same comparator when the signal changes every cycle. Based on the instantaneous binary signal value and SSVTR, only one comparator is connected. The system has individually adjustable delays for each receiver to connect or disconnect the comparator, thereby reducing the time shift effect during transmission of the source synchronous signals. The system may have a multiple differential source of synchronous voltage and time reference signals to compare multiple single signals in the same integrated circuit as a microprocessor or system controller having multiple signals. The system and method provide the benefits of differential signaling in a simple signaling system.

Using the same concept, a complementary source of synchronous reference signals can compare bidirectional single signals. The system may have a control circuit or transmitter for controlling the tracking rate of the signal so that it is a substantial part of the overall signaling period, thereby reducing the output current. The system may have internal impedance matching circuits such as lift resistors or a grounded gate p-channel to accommodate the characteristic impedance of the transmission line at both ends of the connection between the CPU and the cache or between the CPU and the system controller. The system has a comparator pair circuit to convert a single bus with two complementary signals designed to be transmitted and received with comparable differential bus noise immunity to an internal data bus memory, processor, or other wide data bus type integrated circuits. Preferably, the system has a varying size transceiver device having a slow bidirectional voltage and timing on and off system to have similar tracking speeds for all signals in each SSVTR and / SSVTR group and the group of signals being transmitted together. It will further be appreciated that the control signals and address signals may be transmitted on a different channel than the data signals. This allows operation of the control and address channels at a different frequency than that of the data channel, and allows the use of different loads for each channel.

Overview of the drawings

Giant. IA is a block diagram illustrating a prior art RAMBUS-based receiver.

Giant. 1B is a timing diagram illustrating signal levels at a prior art receiver shown in FIG. IA. Giant. 1C is a schematic diagram showing another RAMBUS-based receiver according to the prior art.

Giant. ID is a timing diagram illustrating the operation of the prior art receiver of FIG. 1C.

Giant. 2A is a perspective view of a block diagram illustrating a control and slave system according to the present invention.

Giant. 2B is a block diagram illustrating the system of FIG. 2A having transmission lines with an impedance corresponding to the resistors at the ends.

Giant. 3A is a timing diagram showing differential reference signals SSVTR and / SSVTR relative to signal acquisition times.

Giant. 3B is a timing diagram illustrating SSVTR and / SSVTR relative to a single signal.

Giant. 4 is a high-level diagram illustrating single signal receivers.

Giant. 5 is a flowchart showing a method of transmitting signals from a transmitter over a transmission line to a receiver.

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4

445 44 * 4 V *

4444 44 44 44 «44 444

Giant. 6A is a wiring diagram showing a slow start and slow trip control circuit for all signals.

Giant. 6B is a circuit diagram showing control circuits having adjustable signal tracking speeds and time shift between signals.

Giant. 7A is diagram connection receivers j simple signal shown FIG. 4, in the first embodiment * Giant. 7B is diagram connection receivers simple signal shown FIG. 4 in the second design. Giant. 7C is diagram connection receivers simple signal shown FIG. 4 in the third design. Giant. 7D is diagram connection receivers j simple signal

4 in a fourth embodiment.

Giant. 8A is a circuit diagram showing details of the SSVTR k / SSVTR comparator circuit of FIG. 4.

Giant. 8B is a circuit diagram showing details of the SSVTR k / SSVTR comparator circuit of FIG. 4.

Giant. 9 is a wiring diagram illustrating receivers with individually adjustable delays to avoid time shift during transmission.

Giant. 10 shows the waveforms of the signal and the time shift therebetween. Giant. 11 is a perspective view of the hardware circuitry of the system of FIG. 2.

Giant. 12A is a block diagram showing a system of interconnection from one device to another according to the present invention.

Giant. 12B is a block diagram illustrating the interconnection system of FIG. 12A having impedance matched gate p-channel devices within an integrated circuit.

Giant. 13A is a perspective view of a block diagram illustrating a unidirectional signaling system and a bidirectional signaling system on a single integrated circuit.

Giant. 13B is a perspective view of a block diagram illustrating four signaling systems on a single integrated circuit.

«» ·· ·

Giant. 14A depicts a fixed reference voltage of the prior art having a value around the midpoint of a logical high level and a logical low voltage level.

Giant. 14B shows a complementary reference signal having the same voltage amplitude as any other signal.

Giant. 15A illustrates a differential amplifier that amplifies the difference between a data signal and a reference.

Giant. 15B is a block diagram illustrating control logic.

Giant. 16 is a circuit diagram illustrating a single signal receiver with differential amplifiers gated by a current drop or a receiver activation signal to turn off the current to the receiver when not in use.

Giant. 17 is a timing diagram illustrating the signal transmission time of an application requiring fast bus turn-over from read to write or vice versa.

Giant. 18 is a block diagram illustrating a system of connection from one device to another.

Giant. 19 illustrates a system having multiple buses where signals are received simultaneously.

Giant. 20 is a block diagram illustrating a system having three buses to achieve higher bandwidth.

Giant. 21 shows a prior art system for DRDRAM that uses a clock line having two segments.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides a signaling system and method of high-speed communication on multiplex buses or links from one device to another between a group of VLSI devices and provides lower power consumption compared to the current single signal interface methodology. The signaling system can be used to connect a plurality of storage devices to a multiplexer bus to a memory control unit for a memory device.

- 10 block transmission of data, address and control information. By using multiple buses, devices such as DRAMs, cross-array switches, processors, wide SRAMs, and system controllers can be brought together to achieve bandwidths above four gigabytes per second. Essentially all signals needed for a computer or other digital systems can be sent via this bus. Those skilled in the art will recognize that all devices, such as CPUs in a computer system, need methodologies and bus structures of the system.

Giant. 2A is a perspective view of a block diagram illustrating a system 200 with control devices (transmitters) 205 coupled through a bus architecture (transmission lines) 215 to a plurality of slave devices (receivers) 210 of the present invention. As shown, control device 205 is arranged to communicate, for example, twenty (20) signals, including simple signals S0 to S17, low voltage synchronous voltage and time reference signals SSVTR and / SSVTR from a complementary source, power lines (not shown), and grounding lines (not shown) parallel to the transmission lines 215 to each slave 210. 2a The advantage will be considered that / is used to denote a logical NOT. The signals S0 to S17 may be data, control or address, either multiplex or non-multiplex, as defined by the protocol. There may be other signals, such as clock or initialization, for other purposes required by the protocol or system synchronization.

As shown in Fig. 3A, the SSVTR and / SSVTR signals are flipped each time valid signals are controlled by control device 205. It will be appreciated that the slave device 210 may include a plurality of receivers 405, see Fig. 4, each receiver 405 includes two comparators, one for • »* ·

11 comparing the signal to the SSVTR and the second comparing the signal to the / SSVTR. The binary value of the signal present determines which comparator is connected to the output terminal 420, optionally using an EXCLUSIVE-OR logic with SSVTR and / SSVTR. Until the binary value of SSVTR and / SSVTR is changed, the activated comparator at receiver 405 detects whether a change in the binary signal value has occurred.

For chip-to-chip communication on a bus or device to device, all signals are preferably transmitted substantially simultaneously from the same chip to another chip or group of chips connected to the bus, and preferably have substantially the same load, oscillation, and tracking speed (when signals are transition). For intra-chip communication, the signals are also preferably excited substantially at the same time, from the same region or block to other regions or other blocks on the same chip, and preferably have substantially the same load, amplitude and tracking speed (when the signals are transient). Giant. 19 and 20, described below, illustrate a system and method for ensuring that signals are energized at substantially the same time.

To facilitate extremely high data rates over this external bus, bus cycles are triggered when the SSVTR is low (i.e., / SSVTR is high). All block transmission begins during the cycle when the SSVTR is low and ends when the SSVTR begins to decrease to facilitate receiver preset 405 for the last binary signal value. This allows for even number of bit bursts. When signals need to change direction (due to the multiplex nature of the signals), one or more dead cycles may be required to calm the bus due to delay in propagation or calm of SSVTR and / SSVTR when bidirectional. Giant. 17 described below illustrates bidirectional timing for bus turnover to prevent lost dead cycles.

Ji ι «I ι,«

Giant. 2B is a block diagram illustrating a system 200 (FIG. 2A) having transmission lines 215 with impedance matching external resistors 220 having a terminal resistance equal to their characteristic impedance, preferably at the ends of 50 to 70 ohms. The voltage at the ends is referred to as VTT and is preferably about 1.8 V for an operating voltage of 2.5 V (for VCC of 2.5 V and VSS of 0 V). The rated voltage amplitude is preferably set to less than IV, preferably less than 40% of the supply voltage, and most preferably set to 500 mV. Therefore, as shown in Figure 3A, the output high voltage (VOH) is 1.8V and the output low voltage (VOL) is 1.3V.

Giant. 3A is a timing diagram illustrating complementary SSVTR and / SSVTR reference signals with signal read times. SSVTR initiates at VOL and / SSVTR initiates at VOH. In the first cycle, control device 205 drives all low signals including / SSVTR to VOL simultaneously, and the terminal resistors 220 lift the SSVTR to VOH. Single signals that are high are maintained on the VOH by the terminal resistors. An appropriate reading time, i.e., the reading time of the logical level of the input signal, is after the SSVTR and / SSVTR connection has passed and before the stable time, i.e., when the SSVTR or / SSVTR reaches a steady state at VIH or VIL. The SSVTR and / SSVTR preferably have the same rise and fall times, each rise and fall time being approximately half the cycle time of one of the reference signals.

Giant. 3B is a timing diagram illustrating SSVTR and / SSVTR relative to a single signal. A single signal starts as equal to / SSVTR at high voltage and then changes with / SSVTR to low voltage. The single signal then remains at a low voltage, becoming equal to the SSVTR, and then converted to a high voltage with the SSVTR. The single signal then remains at high voltage, thus becoming equal to / SSVTR.

»V« ·

Fig. 4 is a high-level diagram illustrating a single signal of a slave 210 having a receiver 405 for each signal line 215. Each signal receiver 405 has two comparators 410, one comparator 410a for comparing the input single signal SNx with SSVTR and the second comparator 410b for comparing SNx with / SSVTR. . Both comparators 410 have output terminals selectively connected via switches 415 to output terminal 420. It will be appreciated that the output signal (SN) to output terminal 420 is preferably a full-scale signal (0V to 2.5V).

As mentioned above, SSVTR is initially set to VOL and / SSVTR and SNx are initially set to VOH. SN is initially set to high full-scale output voltage. Accordingly, comparator 410a amplifies the high voltage SNx minus the low voltage SSVTR, thereby providing a high output signal. Comparator 410b amplifies the high voltage SNx minus the high voltage / SSVTR, giving an unknown output signal due to the noise amplification. The choice of switch 415 is controlled by EXCLUSIVE-OR (XOR) logic gates 425. More specifically, the XOR gate 425a compares the full range amplified SSVTR signal (VT) versus the output signal SN and generates a control signal for the control switch 415a. The XOR gate 425b compares the full range / SSVTR (/ VT) against the output signal SN and generates a control signal for the control switch 415b. In this initial state, only the SSVTRs and accordingly the VTs are low, causing the XOR 425a to move the switch 415a to closed. Accordingly, the output (high) of the comparator 410a reaches the output terminal 420. The XOR 425 moves the switch 415b to open, thereby preventing unwanted output signal from the comparator 410b from being input. Receiver 405 is stable.

• «· ♦

According to the example shown in Fig. 3B, a single SNx signal changes to a low voltage. As always, the SSVTR and / SSVTR change in opposite directions. Accordingly, once the SSVTR and / SSVTR have reached a predetermined difference (preferably 250 mV) between each other, the VT and / VT change. Similarly, once the SSVTR and SNx change to a predetermined difference (preferably 250 mV) between each other, the output of the comparator 410a also changes (to a low output voltage). It will be appreciated that the route from the external SNx signal to produce the output SN signal and the full-range VT and / VT signal path each include one comparator 410 or 435 and two inverters 430 or 440. Therefore, each XOR gate 425 receives new input signals based on In this example, as shown in the timing example of FIG. 3B, the SSVTR and / SSVTR reach a predetermined difference at the same time as the SSVTR and SNx reach the same predetermined difference. Accordingly, the XOR 425a will continue to receive the differential inputs, keeping the same switch 415a closed and allowing the low output voltage from comparator 410a to pass to output terminal 420. Receiver 405 is still stable.

Also, according to the example of FIG. 3B, a single SNx signal is not converted. As always, the SSVTR and / SSVTR vary relative to each other. Accordingly, the currently activated comparator 410a continues to drive a low output voltage. When the SSVTR and / SSVTR reach a predetermined difference from each other, but before the SSVTR reaches the same voltage as the SNx (thereby avoiding the possibility of an indeterminate output signal state), the XOR 425a is turned off and the XOR 425b is turned on. It will be appreciated that since the / SSVTR begins to increase, the comparator 410b could generate a low output voltage. Receiver 405 is still stable.

Β Β · «·

ΒΒΒ ΒΒΒ ΒΒΒ «ΒΒΒ ΒΒ ΒΒ ··· ΒΒ Β · ΒΒ

Each receiver 405 can easily detect and amplify very small signals of the order of 100 to 250 mV. If the conversion occurred in a single SNx signal, the output signal SN has a new level that is opposite to its previous signal level. Since both the SSVTR (or / SSVTR) and the single signals have changed, the same comparator 410 is still connected to the signal output terminal. If the simple SNx signals have not changed, then the signal output SN does not change, the comparator 410 connected at the start of the conversion is disconnected from the output after the SSVTR and / SSVTR receiver have amplified their new binary state (VT & / VT) and the second comparator 410 has the opposite / SSVTR (or SSVTR) is connected to provide signal output. The old output level is restored.

It will be appreciated that receiver 405 can be implemented without the use of XORs. This can be accomplished by using the known polarity SSVTR and / SSVTR in the initial cycle and by starting all single signals as high. SSVTR and / SSVTR change in each cycle. Thus, their polarity in each cycle can be determined by verifying the system clock in the synchronous system and defining the start of the cycle in even clock cycles (i.e., the SSVTR is low in the even clock cycle and / SSVTR is high). Then, only the output signal SN is monitored as it connects and disconnects the comparators 410 based on whether the output signal SN changes the state each cycle or not. If the output signal SN changes state, the connected comparator is left alone. If the output signal SN does not change, the connected comparator is disconnected and the second comparator is connected, etc.

It will be further appreciated that the system of the invention allows all signals to be connected to low impedance sources, allows all signals to present voltage and noise conditions substantially differentially in noise immunity, and allows voltage variation to be reduced compared to other work technologies. ·

- 16 with simple signals such as RAMBUS, HSTL or GLT. The low voltage of 0.5 V implemented in this exemplary embodiment allows very high signal speeds with much lower current consumption compared to other single signal processing technologies. Furthermore, it is an advantage that each receiver 405 amplifies single SNx signals during signal conversion without the need for a conventional clock or other time signal except SSVTR, / SSVTR and their amplified versions of VT and / VT.

Giant. 5 is a flowchart illustrating a method 500 of communicating signals from control device 205 over transmission line 215 to receiver 405. Method 500 begins by controlling control device 205 in step 505 to set SSVTR to VOL and all single signals (/ SSVTR and SNx) to VOH, and by setting, in step 510, all single receiver outputs (SN) to the full high range. Receiver 405 at step 515 links the comparator 410a, which compares the SSVTR with each single SNx signal, to the output terminal 420 of the receiver 405. In step 517, the receiver 405 settles all signals on the transmission lines. Steps 505 to 517 are referred to as system initialization.

The control device 205 in step .02.0 simultaneously drives the SSVTR n / SSVTR to its opposite states and all single SNx signals to their desired levels. Receiver 405 at step 530 compares the single SNx signal to SSVTR and / SSVTR in the respective comparators 410. Receiver 405 at step 540 determines whether the single signal has been converted. If this is the case, then the receiver 405 at step 545 passes the result to the output terminal 420 and keeps the same comparator 410 connected to the terminal 420. If this is not the case, then the receiver 405 disconnects the previous comparator 410 at step 550, output terminal 420 and maintains the same output signal (SN). Transmitter 405 in step 555 • · 44 • 4 · ·

4 4 4 4 4

- 17 determines whether the signal burst continues. If so, then the method 500 returns to step 520. Otherwise, the method 500 ends.

Giant. 6A is a schematic diagram illustrating slow switching on and off of the single signal control device 205 in the first embodiment referred to as transmitter 600. The transmitter 600 includes a NMOS downlink device 605 connected to transmission line 610 to accurately match the output amplitude to 500 mV below VTT. The downstream NMOS device 605 includes a downstream NMOS transistor T1 having its source connected to transmission line 610, a collector connected to ground, and its gate connected to a time shift control circuit 620. The time shift control circuit 620 includes a CMOS inverter comprising two transistors T2 and T3, connected between two resistors, R1 and R2. The input to the CMOS inverter is connected to the signal to the control device 625. For example, to generate an SSVTR or / SSVTR, the signal to the control device 625 may be an oscillator. It will be appreciated that the download size may be adjusted using a register (not shown) and a serial port (not shown) during initialization to set the correct voltage amplitude for all variations of the method and apparatus. Other methods can also be used, such as the use of control binding techniques as shown in Hans Schumacher et al. (Less than nanosecond true-ECL CMOS (True-ECL Output Bufer) CMOS), J. Sol State Circuits, Vol. 25 (1), pp. 150-154 (February 1990) Maintaining a current of 20 mA and the existence of parallel 50 ohm terminals at both ends of the transmission line 610 (as controlled by R1 and R2) generates under all conditions In order to minimize the rise and fall times at the output and to minimize reflections, network switching noise when connecting and disconnecting the signal, the shift control circuit 665 controls the pull-down transistor T1 to switch on and off slowly. is 1.6 ns / V with a transition time of 0.8 ns for 500 mV.

For an equally changing, ramp-like signal, the preferred signal tracking rate is four times the sum of the two inverter delays and the EXCLUSIVE-OR delay in the technology. For 0.25 μ CMOS technology with an operating voltage of 2.5 V, the inverter delay is 50 picoseconds and the EXCLUSIVE-OR delay is approximately 120 picoseconds. The preferred tracking speed is about 880 picoseconds. For signals transmitted above 600 MHz, the signal tracking rate is preferably less than 110% of the signal rate. The preferred tracking rate for exponential signals is slightly faster if the signal reaches 75% of its final value earlier than during the transition time. The differential signals preferably cross half through a voltage change. In the path around the voltage change, the signals have a difference of about 250 mV, which can be quickly converted to a large amplitude signal. Preferably, in order to avoid noise amplification and to prevent the signal from being connected to the receiver output after receiving non-transient single signals, the transition time between 75% and the final signal value is greater than the sum of the two inverter delays and

EXCLUSIVE-OR DELAY. It will be appreciated that the tracking speed may be as fast as the amplified noise reaches the output of the comparator 410, the output of which is connected to the output terminal 420. This means that upon receiving the unchanged signal the switch 415 switches the state before the comparator output changes noise-based state. The output of the currently connected comparator 410 approaches an undetermined state (only noise amplified). Switches 415 must switch states before undetermined output becomes available. Another advantage will be that the non-conforming of the device, manufacturing tolerances and signal reflection will affect the rate at which the output of the comparator 410 reaches an undetermined state. As technology improves, gate delay, higher tracking speed and higher signal speed can be achieved.

• φφφ · · · · · φ ··· * · φ · Φ · ·· ·· ΦΦΦ

Giant. 6Β is a schematic diagram illustrating a control device 205 having adjustable signal tracking rates and a time shift between signals for another exemplary embodiment referred to as transmitter 650. Transmitter 650 includes NMOS downlink device 655 connected to transmission line 610 to accurately match the output amplitude to 500 mV below VTT. The NMOS downlink device 655 includes downstream NMOD transistors 660 connected in parallel, each having its source connected to the transmission line 610, its collector connected to ground, and its gate connected to the Time Shift Control circuit 665. The time shift control circuit 665 includes a CMOS inverter comprising two transistors T2 and T3 connected between two sets 670 and 675 of parallel connected resistors. The input to the CMOS inverter is connected to the signal control device 625. The 670 and 675 resistor sets match the rise and fall times. It will be appreciated that the up and down times are preferably as symmetrical as possible to have a midpoint of crossing all signals and sensing all signals by differential receivers to appear in parallel. Achieving symmetry and adjusting the tracking speed and output amplitude can be achieved during the test phase by fusing fuses (not shown) or during initialization on the board by setting a register (not shown).

It will be appreciated that signal change times may be slightly greater than the signal rate. For some heavily loaded buses, the amplitude may be increased to treat transmission losses, and yet the receiver 210 still receives 500 mV for readability to be easy. Another advantage will be that different tracking speeds, exponential transition times and voltage oscillations are possible based on technology, load and reception and resolution delays of the receiver. Even transient times slightly higher than the signaling speed are possible with • ··· «····· · · · · · ♦ ·· ·

- 20 transient signals reaching 90 to 95% of their final value during clustering. Also during testing, the drift between single signals and SSVTR and / SSVTR is adjusted using the size of the NMOS withdrawal and the resistors in the gate ahead of it using well known techniques such as laser fuse blowing or setting the register code to achieve the waveform of the signal as as shown in FIG. 10. As shown in FIG. 10, all single SNx signals should be coincidence or less than 50 ps before the SSVTR and / SSVTR transition. This time offset can be adjusted after testing to be within this range.

Giant. 7A to 7D illustrate an alternative embodiment of each signal receiver 405 of FIG. 4. It will be appreciated that the comparators 410 of the receiver 405 need to operate during each cycle, requiring small acquisition and resolution delays that do not take any input current and do not put any current back into the signal knowledge. A conventional differential amplifier satisfies all these requirements. Referring to Fig. 7A, receiver 210 uses dual differential amplifiers 702, one differential amplifier 702a to compare the SNx signal to the SSVTR, and the other differential amplifier 702b to compare the SNx signal to the / SSVTR. For completeness, a brief overview of the differential amplifiers 702 is given. The differential amplifier 702 is always activated. Based on the channel sizes when the SSVTR voltage is higher than the SNx voltage, more current is routed through the transistor T10, thereby pulling out the output voltage at node 707 (approaching VCC or 2.5 V). When the SSVTR voltage is less than the SNx voltage, more current is drawn through the NMOS transistor Til, thereby pulling down the output voltage at node 707 (approaching VSS or 0 V). The differential amplifier converts the small (0.5 V) input to the large (0 V to 2.5 V) output.

• 999 • 99 ttt 9 9 9 9 * 99 99 99 999

The outputs of the differential amplifiers are amplified and inverted by the inverter 704, pass through the CMOS transmission gates 706 and are coupled together at the node 708. The transmission gates 706 are selectively operated depending on the amplified state of the previous signal (SN) under EXCLUSIVE-OR operation with amplified SSVTR or / SSVTR status, i.e. VT or / VT. The EXCLUSIVE-OR is designed to be stable without short disturbance pulses for small timing variations between Sn, VT and / VT reaching their respective logical levels.

Various embodiments are shown. Giant. 7A depicts always activated differential amplifiers, with only the transmission gates being selectively activated for a small number of devices and a higher rate than the alternative embodiment 700. FIG. 7B illustrates a differential amplifier and transmission gates activated or deactivated simultaneously as an alternative embodiment 720. FIG. Fig. 7C illustrates differential amplifiers that are activated by the same EXCLUSIVE-OR for low current, rapid disabling of the gate gates during transmission of the EXCLUSIVE-OR output, and slowly activating the gate gates after the EXCLUSIVE-OR is stabilized as an alternative embodiment 740. FIG. 7D depicts 1.2-channel P-channel differential amplifiers for lower current applications as an alternative 760. All differential amplifier gates can be deactivated to reduce current when the receiver is not selected or when the device is not selected or when the device is deep in the low current mode. The differential amplifier can be deactivated by switching off the transistor Til.

By using a 1.2V termination and a receiver 405 as shown in FIG. 7D, current consumption can be further reduced by an additional 33%. This means that the voltage oscillation will be from 1.2 V to 0.7 V, which allows decent edges from the lower oscillation and lower.

- 22 power consumption for portable systems. The operating frequency may be comparable to fewer devices on the buses, which is common to portable devices for a smaller shape factor. Transmitter 205 may still be an NMOS downlink TI or parallel link downstream NMOS transistors 660. Receiver operation is similar except that the differential amplifier 706 becomes a mirror image, thereby increasing the gate capacity of the signals going to the P-channel gate for comparable operation by approximately double thanks to the increased size of the p-channel device. Other differential amplifier configurations that rapidly convert small-scale differential signals to large-scale differential signals may alternatively be used in place of the differential amplifiers shown. One skilled in the art will appreciate that another embodiment may use two different VTTs, one for signals equal to 1.8 V with a 500 mV oscillation and the other for oscillating reference signals equal to 1.7 V with a 300 mV oscillation. All signals change simultaneously and have similar rise and fall times. The same transmitter / receiver pair can handle multiple VTT systems.

It will be appreciated that the DC bias point of each differential amplifier in receiver 405 is arranged such that the receiver output voltage 405 is above half of the VCC when both low amplitude voltages (single signal SNx and SSVTR or / SSVTR activated differential amplifier) are close to VIH and below half of the VCC when both low amplitude voltages are close to VIL. This DC bias makes it possible to create the proper edge and protect the output signal SN when a single SNx signal does not change the state and the SSVTR or / SSVTR of the activated differential amplifier closes the differential signal before it is disconnected.

• ·· · 9 · 9 · 999 99 99 99 99

Because the receiver 405 operates during signal conversion for a low-frequency single signal, the concept of set and stable time from a specified time after the signal level reaches VIH / VIL or VREF used in previous signal processing techniques is no longer used. Also, there is no VREF (reference voltage) for comparison with the signal voltage. By eliminating the timing required to set and hold and the timing required to activate the voltage edges for sensing around the VREF, the operating frequency is greatly increased at a lower power consumption. Further, all receivers 405 are self-timer, without the need for a global clock, allowing receivers 405 to be adjusted individually to eliminate transmission time shift at the board or packet level.

Giant. 8A and 8B are schematic diagrams illustrating in detail the comparator circuit 435 of FIG. 4. Each comparator 435 includes a differential amplifier 802 (FIG. 8A) or 852 (FIG. 8B) similar to the differential amplifier 702 of FIG. 7A and multiple inverters 804. (FIG. 8A) or 854 (FIG. 8B) in series. The full-scale output signals of comparators 802 and 852 (VT1, VT2, VT3, / VT1, / VT2 and / VT3) are transmitted to all XOR gates of 425 single signal receivers (Fig. 4). The choice of VT1, VT2 or VT3 is determined by testing the signal rate substantially as well as selecting the generation path of the output signal SN of the receiver 405.

Giant. 9 is a schematic diagram illustrating receivers 405 with individually adjustable delays to eliminate time shift during transmission and convert small swing to large swing using comparators 410. In order to tune the operating frequency or voltage oscillation for optimal operation, each receiver 405 has a register 905 to store data for activating delivery of one of three • · dodání dodání dodání dodání dodání dodání dodání dodání dodání dodání dodání dodání dodání

24 VT1 and / VT1, VT2 and / VT2 or VT3 and / VT3 to XOR gate 425 (Fig. 4).

Giant. 11 is a perspective view of a hardware arrangement of a combined bidirectional signal control device 1100. The control device 1100 includes receivers 405 and return transmitters 1105 coupled together. More specifically, each single signal received as S0 is coupled to a corresponding receiver 405 such as a S0 receiver and to a corresponding transmitter 1105 such as a TO transmitter. Preferably, all single SNx signals may be grouped together with a single pair of reference signals SSVTR and / SSVTR. However, it will be apparent to those skilled in the art that for a given operating frequency, the SSVTR and / SSVTR load and signal imbalance reduce the number of SNx signals that can be grouped together. As seen in Fig. 11, the arrangement is realized such that capacitances, resistances and inductances on the SSVTR and / SSVTR and all single SNx signals are balanced. Since the SSVTR and / SSVTR also lead to all receivers 405, the overall load on the SSVTR and / SSVTR needs to be minimized.

By using devices with very low current dissipation losses and physical crowding, it can be achieved that the bus can be made as short as possible, which in turn allows short propagation times and high data rates. As shown in Fig. 2B, resistor-terminated impedance-controlled transmission lines can operate at 1 GHz signal rates (lns cycle). The transmission line parameters are strongly influenced by the load caused by integrated circuits such as DRAMy, which are mounted on the bus. These ICs add a one-time capacity to the line, both reducing line impedance and reducing transmission speed. In busy environments, the bus impedance is likely to be of the order of 25 ohms and propagation speed will be 7.5 cm / ns. Make sure that the bus is not controlled from «··· • ·

- 25 two devices at the same time, so for buses smaller than about 12 cm, one dead cycle (eg 2 ns) is required to stabilize the bus to switch from one controller to the other controller. With longer buses, more than one cycle may be needed to stabilize the signals before the new transmitter can control the signals. Unlike RAMBUS, the bus length does not reduce the burst mode operating frequency from the same device.

Giant. 12A is a spatial view block diagram illustrating a point-to-point type system 1200 that includes bidirectional control device 1205 coupled via transmission lines 1215 to bidirectional slave device 1210. Transmission lines 1215 include upper signal SNx line 1220, lower signal SNx line 1225, and SSVTR and / SSVTR line 1230. As shown, Fig. 12B is a perspective view of a block diagram illustrating a point-to-point type system 1200 including end resistors 1235 internally using grounded gate P-channel devices. This eliminates the need for space to connect external resistors and reduces costs. It will be appreciated that the terminal resistors 1235 can be realized using internal resistors instead of the grounded gate of the P-channel devices. Termination of both ends by the respective characteristic impedance is advantageous for bidirectional signals on the bus. Because the intra-chip blocks are physically close, impedance modifying resistors are not required. Small lifting devices are sufficient. Similarly, when the connections within the chip are physically close, impedance modifying resistors can be replaced by small lifting devices to reduce cost and current and maintain the same tracking speed.

It will be appreciated that multiple buses are required for devices such as SLDRAM, DDR SDRAM, or various DDR SRAMs where signals are transmitted and received simultaneously. Giant. 13A is a perspective view of a block diagram illustrating a combined one-way and two-way SLDRAM system 1300 on a single integrated circuit. System 1300 includes a control device 1305 (eg, a memory control unit) connected via transmission lines 1315 to slave devices 1310 (eg, to SLDRAMs). Control device 1305 transmits address and control signals over address and control lines 1320 and 1325, transmits and receives data signals over data lines 1330 and 1335, transmits on the SSVTR and / SSVTR 1340 lines the first set of reference signals SSVTR and / SSVTR (i.e., SSVTR0 and (SSVTR0) for examining address and control signals and transmits a second set of reference signals SSVTR and / SSVTR (i.e., SSVTR1 and / SSVTR1) to slaves 1310. The address and control portion of system 1300 organizes the unidirectional signals needed only by slaves 1310. The 1300 is bidirectional, based on whether the control signal specified a READ or WRITE operation.

For SLDRAM, the 40-bit command and address are sent in a packet of four 10-bit words. SSVTR0 and / SSVTR0, which may be referred to as system differential clocks, operate at 500 MHz. A phase locked feedback loop (not shown) is used to lock clock and timing frequencies for various internal purposes and control the data output with SSVTR1 and / SSVTR1 at both edges for a 1 GHz data rate. All high-frequency signals are terminated at both ends of the bus with their characteristic impedances. The termination at the end of the memory control unit may include external resistors, internal resistors or internal grounded gate P-channel devices, since this memory control unit is usually a control device and is fixed. Since the number of components (SLDRAMs) 1310 (which act as slaves) is variable, the components 1310 are preferably terminated by external resistors at the end of the transmission lines. 18-bit bidirectional 94 94 94 94

- 27 data bus 1330 and 1335 operates at the same frequency as the system clock for synchronization and sends data in eight 18-bit words in four clock cycles (8ns) or 2.25 gigabytes / s from a single SLDRAM. It takes care of balancing the load on SSVTRO and / SSVTRO by adding dummy gates and wiring to make it look comparable to SSVTR1 and / SSVTR1. This load balancing causes the tracking speed given by the load to be similar and allows similar edges for all signals.

When a higher bandwidth is required, the system 1350 can use four buses as shown in Figure 14B. Two separate SLDRAM channels 1310 are used with a single memory controller 1305. This arrangement allows a peak data bandwidth of 4.5 gigabytes / s. Although system 1350 does not require a synchronous clock for transmitter 1305 or receiver 1310, system 1350 may use a synchronous clock to transmit data at a particular time and frequency to facilitate testing and usability with existing synchronous DRRM and SRAM protocols. It may be desirable to use on-chip multiplier or slow clock or internal circuit oscillator to transmit data at high frequency without high-speed clock for synchronization to reduce system noise and current. It will be appreciated that those skilled in the art, using the nature of the present invention, can achieve very large, synchronous or asynchronous very broadband systems.

Five concepts are explained in more detail below, which further explain the input and output circuits 210 of FIG. 4,

The first concept concerns the existence of complementary reference signals. As shown in FIG. 14A, prior art systems use a fixed reference voltage VREF whose value is around the midpoint of the logical high voltage level (VOH) and the logical low voltage level (VOL). VREF generator (not

Μ · * · · * * * * * «« ««

28 (shown) typically has a certain DC bias from fluctuations in the power supply used to generate it, the fluctuation being shown as VREFH 'and VREFL. It also has some AC noise due to instantaneous fluctuations in the power supply voltage, ground reflection, capacitive coupling, and inductive coupling with adjacent signals. The differential amplitude to the comparator used in the prior art receiver is indicated by arrows. It should be noted that the worst-case differential signal of the prior art will be of the order of 1/3 to 1/4 of the total voltage amplitude of the signal.

As seen in Fig. 14B, the systems and methods of the invention use a complementary reference signal SSVTR and / SSVTR having the same voltage amplitude as each signal (eg, data or control). In a particularly preferred embodiment, this voltage range is 500 mV with a logical high voltage (VOH) of 1.8 V and a logical low voltage (VOL) of 1.3 V. It will be appreciated that the average of the complementary reference voltages is around the center of the VOH and VOL at any point in time during operation of this signaling system. The signals and the complementary reference signal have the same transition times and voltage surges and are initiated simultaneously from the same source (the same inter-chip communication device or the same general location for intra-chip communication) to be sent to the receiver. In other words, the complementary reference signals look the same as any other signal, but the complementary reference signals are flipped over whenever other signals need to be transmitted. Since the complementary references use current supply and grounding simultaneously, all noise is common mode. Therefore, the variation of the VREF value (VREFH and VREFL) of the signal amplitude required in the prior art is no longer needed in the systems and methods of the present invention. Due to the binary nature of digital signaling, it will always have one complementary reference signal • · Β β · · · · · · · ** ** ** ** ** ** ** ** ** ** ** **

- 29 opposite polarity to the signal at the beginning of the reference signal conversion and at the end of the reference signal transition. Therefore, a single reference value present will have a total oscillation of about 500 mV at a certain time, thus allowing the comparator to sense the signal voltage more easily than the prior art system having only 1/3 to 1/4 of the total signal amplitude. The conversion time of the signal and the reference signal may be half the conversion time required in the prior art to achieve the same differential signal during signal change. It will be apparent to those skilled in the art that for optimal operation, the VOH and VOL should be set somewhere between several hundred mV under power and several hundred mV above ground, with a difference of 500 mV between them. The difference can be further reduced to 200 mV to 300 mV if equipment misalignment is reduced and signals have little or no reflections, especially for intrachip communication.

The second concept concerns the existence of two comparators for each input signal. Referring again to Fig. 4, since the signal is compared to both complementary reference signals, each receiver 210 has two comparators. One compares the SNx signal to the SSVTR and the other compares the SNx signal to the / SSVTR. At the beginning of the burst conversion, the full differential signal comparator at its input is coupled to the receiver output 210 and the second comparator having no differential signal is disconnected from the receiver output 210. This is done by initializing. If the SNx signal and the associated reference signal change, then the comparator quickly senses the signal as a differential amplifier, a fast amplifying signal, and a control output to the opposite state. If the SNx signal does not change (i.e., only the reference signal changes) then the differential input to the comparators that is connected at the start of the reference signal conversion will decrease steadily over the conversion time, possibly until no differential input is provided. Differential input to comparators that is disconnected at

1-14, the start of the conversion of the reference signal will increase steadily over the conversion time, eventually until a full differential signal is provided. The originally coupled comparator without the differential signal at the end of the conversion is disconnected and the originally disconnected comparator with the full differential signal at the end of the conversion is connected. The present invention uses two comparators to sense one signal. Further, the binary nature of the digital signals ensures full signal amplitude on one of the comparators at the beginning of each possible valid conversion.

The third concept concerns initialization. Since only one comparator is connected to the receiver output at a time, it is important for proper operation to have a full differential input comparator connected to the receiver output 210 at the start of the burst. Therefore, all signals SOx to SNx are initialized to the logical upper level of the VOH. Turning off all controllers, initializing SSVTR to VOL, initializing / SSVTR to VOH and connecting signals to terminal resistors or p-channel hoists with their gates on, and with a VTT connected source (VTT is 1.8V) will reduce power consumption current. Receiver outputs 210 for S0 to SN are biased high on the VCC using p-channel device 1615 of Fig. 16 to ensure that control logic (explained below) connects the full differential signal comparator to receiver output 210.

The fourth concept concerns discrimination against signal changes. As known to those skilled in the art, a differential amplifier is characterized in that it amplifies small voltage differences to large voltage differences. The voltage gain is typically 3 to 5 times, based on the size of the device and corresponds to the transistor. The inverter located behind the differential amplifier provides additional amplification to achieve near full swing, depending on the size selection • ···

- 31 devices. The speed of the differential amplifier and inverter when reaching full amplitude depends on the differential signal available at its input. As shown in Fig. ISA, the 1501 differential amplifier (and inverter) can amplify the conversion of both the SNx and SSVTR 1500 very quickly, but when the SNx does not change, the signal to the differential amplifier is reduced only to noise and the speed is much less (based on mismatch and noise). The transforming signal SN '(output of the differential amplifier and inverter) is shown as a dotted line 1503. The area 1502 to the left of the transforming signal 1503 is labeled Change.' The area to the right of the transforming signal SN '1503 is labeled No Change). As mentioned above, when the signal does not change, the amplifier 1501 is limited to noise amplification, which is referred to as the indefinite region 1506. The time period before the amplifier reaches the indefinite region 1506 is referred to as the temporary delay region 1504. The present invention has the advantage of a time delay in that it allows the control logic described below to pass the changing signal to the receiver output and to prevent it from passing an indeterminate signal. By selecting the right device sizes and conversion times, a time delay sufficient to allow the control logic to operate so that the signal change passes but no signal change passes and the resulting indeterminate voltage signal does not pass can be made. It will be appreciated that some indeterminate voltage level can pass as long as it is less than the logical threshold of the XOR gate behind it and the other comparator can quickly restore the voltage level. Another advantage will be that the time delay depends on the signal amplitude, the reference signal conversion time, process non-adaptation, signal reflection, etc.

The fifth concept concerns control logic. Referring to FIG. 15B, the control logic circuit 1550 connects the respective comparator 1555 to the receiver output 1560 and is based on the timing generated by the 444.

- 32 with a differential amplifier using SSVTR, / SSVTR, and present receiver output 1553. Control logic 1550 uses SSVTR, / SSVTR, and present receiver output signal 1553. As shown in Figure 4, initialization of input signals SOx to SNx on the VOH reference signal. / SSVTR on VOH, SSVTR reference on VOL and receiver output signals Ξ0 to ΞΝ on VCC connect respective comparators 410 to receiver output 420 before burst burst. With the transforming signal, the control logic 1550 does not change because the XOR 1565 control logic selects the appropriate amplified reference signal and the output of the signal receiver. Since both the amplified SSVTR reference signal and the SNx conversion and delay paths for the amplified SSVTR reference signal and for the SNx on the XOR 1565 are identical, the XOR 1565 does not switch. Alternatively, if the input signal is not converted, the previous comparator 1555 that was connected is disconnected and the second comparator 1555 that has not been connected is now connected. The output of the signal receiver does not change and is actively controlled by the connected comparator 1555 so as to restore the output level if desired. The control logic 1550 is constructed to appear during a time delay 1504 between the change in signal 1502 and no change in the signal 1506, as explained above.

The control logic is performed using an individual EXCLUSIVE-OR locally for each comparator for higher speed, better adaptation of segmenting time and to improve margins or adjustments for time shifts and misalignment. It would also be possible to have all comparators disconnected from their receiver outputs using SSVTR and / SSVTR timing and one control signal for all the receivers of one bus channel signals so that it appears at the segmenting time during the time delay to reduce the number of devices in the receivers. This would limit the operating bandwidth, since a proper comparator must be connected to the receiver output before starting the next conversion.

94 «

9 «4 4 · 4 4 4 4

944 4 4 4 444

4444 4 * * 4 44 44. 4 44

When all these elements are combined together, the entire signaling system operates with the entire signal SOx to SNx and / SSVTR, starting at VOH, the entire output of the signal receiver is pre-charged to VCC, and SSVTR starting at VOL. Before initiating a burst of signal pulses by converting complementary reference signals, all the differential signal comparators (SNx and SSVTR) are connected to the receiver outputs. For signal conversion, the control logic allows the signals to drive the output to the opposite edge of the voltage range. For signals that do not change, the control logic disconnects the signals from the current comparator to another comparator to hold or restore the receiver output. The next conversion is chained to continue with the overlap of the control logic transformations until the control logic delay limits the bandwidth or time interval to allow the subsequent conversion.

As shown in Fig. 16, the single signal receiver has differential amplifiers with a gate operated current drop signal or a receiver activating signal to turn off the current to the receiver when not in use. In contrast to FIG. 7A, the inverters were replaced with NAND 1610 gates connected to a current drop signal or a receiver activation signal. Further, the lift transistor 1615 was coupled to a node 708 on its collector, a VCC to its source, and a current drop or receiver enable signal on its gate to bias the VCC at the SN. The NAND 1615 behind the differential amplifiers also achieves the correct polarity at the SN to initiate a burst cycle. The required initial state is to preset the SNX high, with the SNx pulled up by the terminal resistor or pullout device on the signal line and pulling the SSVTR down and / SSVTR up. The rest of the receiver operation is already described. The P-channel device at the common gateway output node is designed to quickly generate a high bias at the node 708, if necessary, during the node 708. ··

- 34 current rise or when the EXCLUSIVE-OR outputs have not reached stable levels.

By using devices with very low current dissipation losses and high physical crowding, the bus can be made as short as possible, which in turn allows for short propagation times and high data rates. Controlled impedance-terminated transmission lines, as shown in Figure 12, can operate at signal speeds of 1 GHz (Ins) or higher. The transmission line parameters are strongly influenced by the load caused by integrated circuits, such as FRAMES, mounted on the bus. These ICs add one-time capacities to the line, reducing line impedance and reducing transmission speed. In a load environment, the bus impedance is likely to be of the order of 25 ohms and propagation speed will be 7.5 cm / ns. In an application requiring a fast bus turn from read to write and vice versa, as shown in Fig. 17, the signal conversion time is selected to be about 25 to 30% of the signal speed (half the cycle time). The gain is initiated at an additional 25 to 30% signal speed. The control circuit is turned off to stabilize the signals at about an additional 25 to 30% of the signal speed. It will be appreciated that the next cycle where the signal or data direction is reversed can be performed without loss of bus efficiency, where the devices are close together and the bus stabilization time is less than half the signal speed.

Giant. 18 is a perspective view of the connection from points of one device to points of another device. By incorporating terminal resistors internally using grounded gate P-channel devices, high performance systems can be built to connect the points of one device to the points of the other device as shown in Figure 13B. The internal incorporation of the terminal resistors eliminates the need for space to connect external resistors and reduces the "a" and "aaa a * aaa"

- 35 costs. It is also possible to close the gate of the P-channel devices on the transmitting side to reduce the current required to discharge the signal lines to the desired voltage. Both the CPU and the memory control unit have P-channel terminal devices whose sizes can be selected to equal the characteristic line impedance when their gates are at ground potential. The gates of the P-channel devices use a signal that is complementary to the receiver activation to deactivate the receiver end and the transmitter end. This switching can be done while the receiver is preset to a high value and before initiating a burst of pulses on the signal lines. Internal resistors can also be used in place of grounded gate channel devices. By using multiple buses as described in the next section, the bus width to the memory controller can be reduced to 32 (36) from 64 (72) or the bandwidth can be greatly increased. The connection at the back of the cache to the CPU cache can also be accelerated, the number of pins on the CPU can be reduced, and PBSRAM can be changed from X36 to X18, reducing size and cost.

Giant. 19 depicts a system 1900 having a plurality of buses for devices such as SLDRAM, DDR SDRAM, or DDR SRAM, where signals are received simultaneously. The system clock bus 1920 starts from the clock source 1915 at the end opposite the memory control unit 1905, is connected to all 1910 devices whose data outputs are connected to the bus 1920, and ends at the memory control unit 1905. The load on the clock signal is adapted to the load on the data output and the reference signals SSVTR1 and / SSVTR1. It will be appreciated that the clock pulses may be differential (preferably) or simple, depending on the clock frequency and system requirements. The clock voltage amplitude may be similar to SSVTR and / SSVTR to have a similar receiver. To keep the delay equal, * · Β ·

BBB BBB BBB BBB BBB

- 36 bus path length 1920 hours is adapted to the path length of the reference signals SSVTR1 and / SSVTR1. The clock source 1915 introduces SSVTR1, / SSVTR1, and DDRDRAM data at different times depending on their location on the bus 1920, so that the data, SSVTR1 and / SSVTR1 arrive at control unit 1905 roughly simultaneously regardless of which DDRDRAM data controls. Each DDRDRAM could possibly use a DLL (Delay Lock Loop) to reduce the 1915 clock data delay if needed for synchronization on the 1905 controller. To remove another pin in the clock system For example, in pulses where data transfer is predictable, a DLL can be used to generate / SSVTR1 having the same timing and voltage parameters but opposite polarity at the receiver end. The DLL would reproduce clocks in all folders (including the 1905 controller and the 1910 DDRDRAMs). The control unit 1905 would be aware of a cycle in which the arrival of the data and the reference signal SSVTR1 is predicted. After initializing the write cycle with address and command signals, DDRDRAM should know the cycle in which the input data will arrive.

The DLL passes the / SSVTR1 signal only when the signal is needed for a particular component. Address and command lines can be grouped with SSVTR0 and / SSVTR0. The address and control bus unidirectionally transmits the input signals from the memory control unit 1905 to the DDRDRAMs 1910. The 10-bit command and the address are sent in as a 2-bit command and an 8-bit address. The 2-bit command is executed using / CE and / RAS on one signal at the two edges of SSVTR0 and / SSVTR0 and the other signal for / CAS and / WE. The 8-bit address at the two edges gives up to 16 bits of the line address appearing with / CE and / RAS or up to 16 bits of the column and block address appearing with / CE and / CAS for the read cycle. The write cycle is performed with 16 bits of column and block addresses with / CE, / CAS, and / WE. SSVTR0 and / SSVTR0 may be system clock derivatives (differential) and operate at the same or multiple system clock frequencies. As explained above, the DLL is «1» I. · I 'ti II ti · I * «·

37 may be used to lock the clock frequency in the memory control unit 1905 for various internal purposes to control command and address signals during a read request and to control data input, SSVTR1 and / SSVTR1 for write requests.

The invention is further distinguished from signal handling in RAMBUS using different reference signals for data inputs (SSVTR1 and / SSVTR1) and for address and control (SSVTRO and / SSVTRO). In RAMBUS, all signals that arrive in RDRAM are scanned on a single clock basis, while in the present invention, the control signals and address signals are on a different channel than the data signals. This allows the control and address signal channel to run at a different frequency than the data channel. All unidirectional high frequency signals (address and control signals) are terminated by their characteristic impedance at the end of the bus from control unit 1905. Since control unit 1905 is typically a control device and is usually mounted, all bidirectional signals (data signals) terminate at the control end. units by external or internal resistance or internal grounded gate of P-channel device. It will be appreciated that, in order to reduce the current, the terminating P-channel device may be turned off during a data write cycle. Termination on the control unit side is possible and can be a high resistance around 10 times the characteristic impedance. Since the number of memory components, i.e., slaves, is variable, the memory components are preferably terminated by an external resistor at the end of the transmission line. The 18-bit bidirectional data bus preferably operates at the same frequency as the system clock for synchronization and preferably transmits data from a single DDRDRAM in four 18-bit words in two clock cycles (4 ns) or 2.25 gigabytes / s.

It is dedicated to adjusting the load on SSVTRO and / SSVTRO by adding dummy gates and wiring to make it look comparable to SSVTR1 and / SSVTR1. This load adjustment makes • ···

- 38 tracking speeds similar and allows similar margins for all signals. When higher bandwidth is required, three busses can be used as shown in Fig. 20. Two separate DDRDRAM channels are used with a single memory controller. This configuration allows data bandwidth at a peak of 4.5 gigabytes / s. Address and command signals can be shared between two channels on SSVTRO and / SSVTRO. The clock and data are split to have a 36-bit data bus using SSVTR1, / SSVTR1, SSVTR2 & / SSVTR2. This saves pins compared to the two channel RDRAMs of the prior art.)

Although the invention does not require a synchronous clock for a transmitter or receiver, it can use a synchronous clock to transmit data at a particular time and frequency to facilitate testing and is useful with existing synchronous DRAM and SRAM protocols. It may be desirable to use a chip-mounted slow clock multiplier or an internal oscillator circuit to transmit data at a high frequency without a high-speed clock for synchronization to reduce noise and current in the system. Those skilled in the art can construct different sizes of synchronous or asynchronous broadband systems according to the above information.

The above description of particularly preferred embodiments of the present invention are exemplary only, and other variations and modifications of the above-described embodiments and methods are possible in light of the foregoing. For example, even though the system and method have been described as transmitting SSVTR and / SSVTR from the control unit 205 to the receiving unit 405, it will be apparent to one skilled in the art that only one reference signal can be transmitted and a complementary signal can be generated on the receiving unit 405. Alternatively, this technique can also be applied to other technologies, such as bipolar or gallium arsenide, which have similar switching devices and gates. Components by • ···

39 of the present invention may be implemented using a programmed digital general purpose computer using application-specific integrated circuits or using a network of interconnected conventional components and circuits. The embodiments described herein are not intended to be exhaustive or to limit the whole subject matter. The present invention is limited only by the following claims.

Claims (12)

PATENT CLAIMS A method for detecting a conversion between an incoming signal and a preceding signal, comprising the steps of obtaining an oscillating reference signal, receiving an input signal, and comparing the oscillating reference signal with an input signal to detect a conversion in the input signal relative to the previous signal. The method of claim 1, wherein the step of comparing comprises generating a first result and further comprising generating a control signal based on the preceding signal to control the passage of the first result as an output signal. The method of claim 2, wherein the step of generating the pilot signal comprises comparing the oscillating reference signal and the output signal. The method of claim 3, wherein the first result manipulates the output signal from the previous signal to the first result, and the step of generating the pilot signal comprises comparing the oscillating reference signal and the output signal while the output signal is still logically equal to the previous signal. The method of claim 3, wherein the first result manipulates the output signal from the previous signal to the first result and; the step of generating the pilot signal comprises comparing the oscillating reference signal and the output signal after the output signal logically equals the first result. The method of claim 1, wherein the input signal is a single signal. The method of claim 1, wherein the oscillating reference signal is synchronous with the input signal. The method of claim 1, wherein the oscillating reference signal provides voltage and time attributes. The method of claim 1, wherein the oscillating reference signal is negated. The method of claim 1, further comprising the steps of obtaining an oscillating reference complementary signal and comparing the complementary signal against the instantaneous input signal and against the previous signal to detect conversion in the input signal relative to the previous signal. The method of claim 1, wherein the oscillating reference signal comprises an oscillating source of synchronous voltage and a time reference signal having a tracking rate substantially equal to half the cycle time of the oscillating reference signal. ♦ 999 • 9 • 9 9 9 9 9 «99 • 9 * 9 99 99 9« · 99 99 A system for detecting the conversion between an input signal and a preceding signal, comprising a first input terminal for receiving an oscillating reference signal and a second input terminal for receiving an input signal, an output terminal providing an output signal logically equal to the previous signal, a first comparator connected to a first and a second input terminal for comparing the reference and input signals to produce a first result, and a first controller coupled to the first comparator to connect the first result to the output terminal based on the previous signal. System according to claim 12, characterized in that the first control unit compares the oscillating reference signal and the output signal. 14. The system of claim 13 wherein the first result is coupled to an output terminal to manipulate the output signal from the previous signal to the first result and the first control unit is coupled to compare the oscillating reference signal and the output signal while the output signal is still logically equal. the previous signal. 15. The system of claim 13 wherein the first result is coupled to an output terminal to manipulate the output signal from the previous signal to the first result, and the first control unit is coupled to compare the oscillating reference and output signals after the output signal logically equals the first. result. + · «· I · · · · 9 9 9 «99 *« 999 99 99 « 16. The system of claim 12 wherein the input signal is a single signal. 17. The system of claim 12 wherein the oscillating reference signal is synchronous with the input signal. The system of claim oscillating reference attributes. 12, the signal provides voltage by means of a timer System according to claim oscillating reference 12 indicating the signal is negated. with that The system of claim 12, wherein the oscillating reference signal comprises an oscillating source of synchronous voltage and timing reference signals having a tracking rate substantially equal to one half of the cycle time of the oscillating reference signal. 21. The system of claim 12, further comprising a third input terminal for receiving an oscillating reference complementary signal, a second comparator connected to the second and third input terminals for comparing the complementary signal and the input signal to produce a second result, and a second control unit connected to the second a comparator for connecting the second comparator to the output terminal based on the previous signal. * ··· * 4 · 4 · 4 4 · 4 444 · 4 · 22. A system for detecting the conversion between an input signal and a previous signal, characterized in that it comprises an output terminal providing an output signal logically equal to the previous signal, a first amplifier for amplifying the difference between the input signal and the oscillating reference signal to produce a first result; a second amplifier for amplifying the difference between the signal and the complementary signal of the oscillating reference signal to produce a second result, a first switch connected to the first amplifier to connect the first result to the output terminal based on the first criterion based on the second criterion, a first control unit for controlling the first criterion based on the comparison of the reference signal and the output signal and a second control unit for controlling the second criterion is based on a comparison of complementary signal and the output signal. 23. The system of claim 22 wherein the first switch connects the first amplifier to an output terminal to manipulate the output signal from the previous signal to the first result, the input signal is logically opposite to the previous signal, the first control unit is connected to compare the reference signal and the output signal, while the output signal is still logically equal to the previous signal, and the second control unit is connected to compare the complementary signal and the output signal, while the output signal is still logically equal to the previous signal. • ··· 4 4 4 ** · · · ··· 44 44 · ··· ·· ··· The system of claim 22, wherein the first switch connects the first amplifier to an output terminal to manipulate the output signal from the previous signal to the first result, the input signal is logically equal to the previous signal, the first controller is connected to compare the reference signal and the output the signal, after the output signal logically equals the first result and the second control unit is coupled to compare the complementary signal a. the output signal after the output signal logically equals the first result. 25. The system of claim 22 wherein the input signal is a single signal. 26. The system of claim 22 wherein the reference signal is synchronous with an input signal. 27. The system of claim 22 wherein the reference signal provides voltage and timing attributes. 28. The system of claim 22, wherein the reference signal is negated. 29. The system of claim 22 wherein the reference signal comprises an oscillating source of synchronous voltage and timing reference signals having a tracking rate substantially equal to one half the cycle time of the oscillating reference signal. 30. A communication system characterized in that it comprises * ·· ♦ φφφφφφφ ·φ ·φφφφφφφφφφ φφφφφφφφφφ ·· - a transmitter for transmitting an oscillating source of synchronous voltage and time reference signals and a new signal to a receiver, transmission lines connected to a transmitter for transmitting a reference signal and a new signal to a receiver, and a receiver connected to transmission lines to obtain a previous signal for receiving a reference signal and a new signal and for detecting a conversion between the new signal and the previous signal versus the reference signal. The system of claim 30, wherein the transmitter further transmits the complement of the oscillating reference signal to the receiver, the transmission lines carry the complement to the receiver, and the receiver detects a conversion based on a comparison of the new signal and the previous signal versus the compel. 32. The system of claim 30, wherein the receiver comprises A first and a second input terminal for receiving, respectively, an oscillating reference signal and an input signal, an output terminal providing an output signal logically equal to the previous signal, a first comparator connected to the first and second input terminals for comparing the reference signal and the input signal to produce a first result; a first controller coupled to the first comparator for coupling the first result to the output terminal based on the previous signal. 33. The system of claim 32 wherein the first controller compares the oscillating reference signal and the output signal. »·· 9 9 9 9999 · * • 9 · 9999 34. The system of claim 33 wherein the first result is coupled to the output terminal to manipulate the output signal from the previous signal to the first result and the first control unit is coupled to compare the oscillating signal and the output signal, while the output signal is still logically equal to the previous signal. 35. The system of claim 33 wherein the first result is coupled to the output terminal to manipulate the output signal from the previous signal to the first result and the first controller is coupled to compare the oscillating reference signal and the output signal after the output the signal logically equals the first result. 36. The system of claim 32 wherein the input signal is a single signal. 37. The system of claim 32, wherein the oscillating reference signal is synchronous with the input signal. The system of claim oscillating reference attributes. 32 characterized by the signal provided by the voltage and timer The system of claim 32, wherein the oscillating reference signal is negated. that 32, the signal comprising: an oscillating source System according to claim oscillating reference • · ·· 48 a synchronous voltage and timing reference signal having a tracking rate substantially equal to one half the cycle time of the oscillating reference signal. 41. The system of claim 32, further comprising a third input terminal for receiving an oscillating reference complementary signal, a second comparator connected to the second and third input terminals for comparing the complementary signal and the input signal to produce a second result, and a second control unit connected to the second comparators to connect the second comparators to the output terminal based on the previous signal. 42. The system of claim 30, wherein the transmitter includes a memory control unit and the receiver includes a memory. 43. The system of claim 30, wherein the transmitter comprises a microprocessor and the receiver comprises a system controller. 44. The system of claim 43, wherein the system controller comprises a memory controller. 45. A signal receiver system for detecting a conversion from a previous signal to a next signal, characterized in that it comprises an output terminal providing an output signal logically equal to the previous signal, a first receiver comprising: 9 9 9 9 9 9999 99 99 999 99 999 49 a first comparator for comparing the oscillating reference signal to a subsequent signal to produce a first result, a first switch connected to the first comparator for connecting the first result to an output terminal, and a first controller coupled to the first switch for comparing the oscillating reference signal to the output signal to produce the control signal for controlling the first switch and a second receiver connected in parallel to the first receiver, including a second comparator for comparing the oscillating reference complementary signal to the next signal to produce a second result, a second switch connected to the second comparator for connecting the second result to the output terminal and a second control unit connected to a second switch for comparing the oscillating reference complementary signal to the output signal to form control signal for controlling the second switch. 46. The signal receiver system of claim 45, wherein the first result is coupled to an output terminal to manipulate the output signal from the previous signal to the first result, the first control unit being coupled to compare the oscillating reference signal and the output signal while the output signal is still logically equal to the previous signal, and the second control unit is coupled to compare the complementary signal and the output signal, while the output signal is still logically equal to the previous signal. * 4 · 4 * · 4 · · 4 4 · · »· 4 4 4 4 4 4 44 ··· - 50 47. The system of claim 45 wherein the first result is coupled to an output terminal to manipulate the output signal from the previous signal to the first result, the first control unit being coupled to compare the oscillating reference signal and the output signal after the output signal logically equal to the first result and the second control unit is coupled to compare the complementary signal and the output signal after the output signal logically equals the first result. 48. A transmission system comprising a generator for generating an oscillating synchronous voltage source and a timing reference having a tracking rate of about half the cycle period of the oscillating reference signal, and a transmitter connected to the generator for transmitting the signal and oscillating reference signal to the receiver. . 49. A method of comparing an incoming signal with a preceding signal comprising the steps of obtaining an oscillating reference signal and its complementary signal, receiving an input signal, comparing the oscillating reference signal with an input signal in the first comparator to produce a first result, comparing a complementary signal with an input signal in the second comparator to produce a second result, using a control signal based on the previous signal to control whether the first result or the second result passes as the output signal. 50. The method of claim 49 wherein ♦ 9 51 the previous signal has previously passed as the output signal through the first comparator, the input signal is logically the same as the previous signal, and the control signal allows the second result to pass as the output signal. 51. The method of claim 49, wherein the previous signal has previously passed as the output signal through the first comparator, the input signal is logically opposite to the previous signal, and the control signal allows the first result to pass as the output signal. 52. A method of transmitting and receiving a plurality of small-scale single signals comprising transmitting a plurality of small-scale single signals from a source to a receiver, transmitting substantially concurrently from a source to a receiver of a pair of complementary, oscillating reference signals having substantially the same tracking speed when the single signals converting, receiving a group of signals and oscillating reference signals at the receiver, producing an output by comparing the oscillating reference signal signals, connecting the output to the receiver output terminal when the signal is converted, and disconnecting the output from the receiver output terminal when the signal is not converted. 53. The method of claim 52, wherein the source is connected to a receiver via a transmission line to a 9 9 9 line. 9 · 9 * 9 999 9999 «10 99 99 99 99 - 52 bus, which is terminated at both ends by the characteristic impedance of the transmission line. 54. The method of claim 52, wherein the source is connected to a receiver by connecting from one device to another device that terminates at both ends within. 55. The method of claim 52 wherein the source includes a device block and the receiver includes another block of the same device with p-channel lift outlets inside the device. 56. The method of claim 52, wherein the signal has a small amplitude less than 1 V. 57. The method of claim 52, wherein the signal has a small amplitude of less than 40% of the supply voltage. 58. The method of claim 52, wherein the signal has a tracking rate of less than 110% of the signal rate for signals transmitted above 600 MHz. 59. The method of claim 52, wherein the oscillating reference signals have substantially the same amplitude. 60. The method of claim 52 wherein the oscillating reference signals have substantially the same load. 61. A method of transmitting and receiving a plurality of low-voltage single signals comprising the steps of transmitting a plurality of low-voltage single signals from a source to a receiver comprising two comparators and an output terminal. 53 transmitting substantially parallel from the source to the receiver a pair of complementary, oscillating, reference signals having substantially the same tracking rate when single signals are transforming, receiving a plurality of signals and oscillating reference signals at the receiver, connecting only one of the comparators to the output terminal based instantaneous logic values at the output terminal and instantaneous values from a single oscillating, reference signal; and disconnecting the second comparator. 62. The method of claim 61, wherein the connecting step comprises connecting only one comparator to the output terminal when the single signal changes. 63. The method of claim 61, wherein the connecting step includes disconnecting only one comparator and connecting the second comparator when the single signal does not change. 64. The method of claim 63 wherein the second comparator provides an output signal that restores the instantaneous logic value at the output terminal. 65. The method of claim 61, wherein the comparators compare single signals to oscillating reference signals to produce output signals. 66. The method of claim 64, wherein only one comparator senses single signals in differential mode with the same noise immunity as differential signals when single signals change. • ··· • - 54 ·· ··· ·· ·· 67. The method of claim 64 wherein the second comparator senses single signals in differential mode with the same noise immunity as differential signals when single signals do not change. 68. The method of claim 52, wherein the source comprises a device block and the receiver includes another block with channel lifts inside the device. 69. A system comprising a control bus having an end at a control device and an end at a slave device, a first reference bus having an end at a control device and an end at a slave device, a first reference signal transmitter coupled to an end at a control device a first reference signal apparatus for transmitting an oscillating reference signal, a data bus having an end at the control device and an end at the slave, a second reference signal bus having an end at the control device and an end at the slave, a second reference signal transmitter connected to the end at the bus control device a second reference signal for transmitting an oscillating reference signal thereto, a third reference signal transmitter coupled to an end of the second slave bus slave; a signal for transmitting an oscillating reference signal thereto, a control device coupled to an end at a control bus control device for transmitting a control signal to a control bus coupled to an end at a data bus control device to transmit the first data signal associated with the control signal to the data bus; data • ··· - a 55 signal in response to a control signal from the data bus and connected to the end at the bus control device of the second reference signal to receive and use an oscillating reference signal from the third reference signal transmitter to detect conversion in the second data signal; a control bus for receiving a control signal connected to an end at a slave of the first reference signal for receiving and using an oscillating reference signal from a first reference signal transmitter to detect a conversion in a control signal connected to an end at a slave of the data bus for receiving a first a data signal associated with the control signal from the control device and for transmitting a second data signal corresponding to the control signal to the control signal; a control device and connected to the end of the slave device of the second reference signal to receive and use an oscillating reference signal from the second reference signal transmitter to detect a conversion in the first data signal. 70. The system of claim 69 wherein the control bus has a first load and the data bus has a second load. 71. The system of claim 70 wherein the first load is equal to the second load. 72. The system of claim 70 wherein the first load is different from the second load. 73. The system of claim 69 further comprising a second data bus for transmitting a third data signal associated with the control signal. Β ·· * · 74. The system of claim 69 wherein each control bus, first reference signal bus, data bus, and second reference signal bus has a terminal resistor internally at the control device end and an external terminal resistor at the slave device end. 75. The system of claim 69, further comprising a second slave coupled to the control bus for receiving a control signal from the control device coupled to the first reference signal bus for receiving an oscillating reference signal from the first reference signal transmitter coupled to the receive data bus. data signals from the control device and transmitting the data signals to the control device and connected to the second reference signal bus to receive an oscillating reference signal from the second reference signal transmitter. 76. The system of claim 75 further comprising a clock bus connecting the first slave to the second slave and again to the control device and a clock source for generating a clock signal on the clock bus to activate substantially simultaneous reception of signals from the first and second slaves device to the control device. 77. The method comprising using a control device to transmit a control signal via the control bus to the first slave, transmitting the first oscillating reference signal to detect transformations in the control signal via the first reference signal bus to the first slave; 9 9 9 9 9 9999 «9 ·· ···» ♦ 999 57 using a control device to transmit the first data signal associated with the control signal via the data bus of the first data signals to the first slave and transmitting the second oscillating reference signal to detect conversions in the first data signal through the second reference signal bus to the first slave. 78. The method of claim 77, further comprising applying a first load on the control bus and applying a second load on the first data bus. 79. The method of claim 78 wherein the first load is equal to the second load. 80. The method of claim 78 wherein the first load is different from the second load. 81. The method of claim 77, further comprising using a control device to transmit a second data signal associated with the control signal via a bus of second data signals to the first slave. 82. The method of claim 77 further comprising terminating each of the control buses, i.e., the first reference signal bus, the first data signal bus, and the second reference signal bus, with a terminal resistor at one end and externally at the other end. 83. The method of claim 77, further comprising providing a second subordinate device between the control device and the first subordinate device. Providing a clock bus connected from the first slave to the second slave and then again to the master and generating a clock signal on the clock bus to activate substantially simultaneous reception of signals at the master from the first and second slaves. 84. The method comprising receiving a control signal through a control bus from a control device, receiving a first oscillating reference signal to detect transformations in the control signal via a first reference signal bus, receiving a first data signal associated with the control signal via a first data signal bus from and receiving a second oscillating reference signal for detecting transformations in the first data signal via the second reference signal bus. 85. The method comprising using a control device to transmit a control signal via the control bus to the first slave, transmitting the first oscillating reference signal to detect transformations in the control signal via the first reference signal bus to the first slave, using the control device to receive a first data signal responsible for the control signal via a bus of the first data signals from the first slave and using the control device to receive a second oscillating reference signal to detect transformations in the first data - 59 * ··· ··· ·· • · ····· via the second reference signal bus from the first slave. 86. The method of claim 85, further comprising using a first load for the control bus and using a second load for the first data bus. 87. The method of claim 86 wherein the first load is equal to the second load. 88. The method of claim 86 wherein the first load is different from the second load. 89. The method of claim 85, further comprising receiving a second data signal responsive to the control signal via a second data signal bus from the first slave. 90. The method of claim 85 further comprising terminating each control bus, the first reference signal bus, the first data signal bus, and the second data signal bus with a terminal resistor internally at one end and externally at the other end. 91. The method of claim 85 further comprising providing a second slave device between the control device and the first slave device, providing a clock bus connected from the first slave device to the second slave device and then to the control device, and 4 4 4 4 4 444 444 44 444 44 444 Generating a clock signal on the clock bus to allow substantially simultaneous reception of signals from the first and second slave devices to the control device. 92. The method comprising receiving a control signal via a control bus from a control device, receiving a first oscillating reference signal to detect transformations in the control signal through a bus of the first reference signal, transmitting a data signal corresponding to the control signal via a data bus to the control device; transmitting a second oscillating reference signal to detect transformations in the data signal via the second reference signal bus to the control device. 93. A system comprising a control bus port, a first reference signal bus port, a first reference signal transmitter connected to a first reference signal bus port for transmitting an oscillating reference signal, a first data signal bus port, a second reference signal bus port, a second transmitter signal a reference signal coupled to the bus port of the second reference signals for transmitting the oscillating reference signals, and a control device coupled to the control bus port for transmitting control signals to the control bus port connected to the bus port of the first data signal for transmitting the first data signal associated with the control signal to port bus of the first data signals and for receiving the second data signals responsive to the control signal; • · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · Η a signal from the bus and the first data signal port connected to the second bus for receiving reference signals and use the input oscillating reference signals from the second bus port reference signals to detect the conversion in the second data signal. 94. The system of claim 93 wherein the control bus port has a first load and the data bus port has a second load. 95. The system of claim 94, wherein said system comprises: by that first the load is equal to the other load. 96. The system of claim 94 characterized by that first the load is different from second load. 97. The system of claim 93 further comprising a second data signal bus port coupled to the control device, wherein the control device transmits a third data signal associated with the control signal to the second data signal bus port and receives a fourth data signal corresponding to the control signal from the second signal. bus port of the second data signal. 98. The system of claim 93 wherein each of the control bus ports, i.e., the first reference signal bus port, the data bus port, and the second reference signal bus port, have an internal terminal resistor. 99. The system of claim 92 further comprising a slave connected to the control bus port for receiving a control signal from the control device connected to the bus port of the first reference signal to receive 999. 9 9 9 9 9 9 9 * · • «99 99 99 999 99 999 62 a first oscillating reference signal from a first reference signal transmitter connected to the bus port of the first data signal to receive the first data signal z, and for transmitting the second data signal to the control device and connected to the bus port of the second reference signal to receive the second oscillating reference signal second reference transmitter. 100. The system of claim 99, further comprising a clock bus port for receiving a clock signal via the clock bus port from the slave. 101. A system comprising a control bus port, a first reference signal bus port, a data signal bus port, a second reference signal bus port, a first reference signal transmitter connected to a second reference signal bus port for transmitting an oscillating reference signal. a second reference signal bus port and a first slave connected to a control bus port for receiving a control signal from the control bus port connected to the first reference signal bus port for receiving and using an oscillating reference signal from the first reference signal bus port to detect a conversion in the control signal a signal coupled to the data bus port to receive the first data signal associated with the control signal from the data bus port and to transmit a second data signal responsive to the and a control signal to the data bus port and connected to the bus port of the second reference signal for receiving and using an oscillating BBB · Β Β Β Β Β · Β · ΒΒ ·· • · - 63 Β · · Β Β ΒΒ A BBB reference signal from the bus port of the second reference signal to detect conversion in the data signal. 102. The system of claim 101 wherein the control bus port has a first load and the data bus port has a second load. 103. The system of claim 102 wherein the first load is equal to the second load. 104. The system of claim 102 wherein the first load is different from the second load. 105. The system of claim 101, further comprising a second signal bus port coupled to the first slave to receive a third data signal associated with the control signal and to transmit a fourth data signal corresponding to the control signal. 106. The system of claim 101 wherein each of the control bus ports, the first reference signal bus port, the data bus port, and the second reference signal bus port have an external terminal resistance. 107. The system of claim 101, further comprising a clock bus port and a clock source for generating a clock signal from the clock bus port to the control device. 108. A system comprising means for transmitting a control signal via a control bus to a first slave device; Φφφ means for transmitting a first oscillating reference signal for detecting transformations in a control signal via a first reference signal bus to a first slave, means for transmitting a first data signal associated with a control signal via a first data bus to a first slave, and means for transmitting a second oscillating reference signal for detecting transformations in the first data signal through the second reference signal bus to the first slave. 109. A system comprising means for receiving a control signal via a control bus from a control device, means for receiving a first oscillating reference signal for detecting transformations in a control signal through a bus of a first reference signal, means for receiving a first data signal associated with a control signal via a first data bus from the control device, and means for receiving a second oscillating reference signal for detecting transformations in the first data signal across the bus of the second reference signal. 110. A system comprising: means for transmitting a pilot signal over the master bus to the first slave, means for transmitting a first oscillating reference signal to detect transformations in the pilot signal through the first reference bus to the first slave, A * ·· I A « Means for receiving a first data signal responsive to the control signal via the first data bus from the first slave and means for receiving a second oscillating reference signal to detect conversions in the first data signal through the second reference signal bus from the first slave. 111. A system comprising means for receiving a control signal via a control bus from a control device, means for receiving a first oscillating reference signal for detecting transformations in a control signal through a first reference bus, means for transmitting a data signal responsive to the control signal via and means for transmitting a second oscillating reference signal for detecting transformations in the data signal through the second reference signal bus to the control device.