MXPA00006702A - Atm processor for the inputs and outputs of a switch - Google Patents

Abstract

The Asynchronous Transfer Mode (ATM) Processor serves as input and output interface to an ATM switch. The circuit has two operating modes, as converter of Cells to Microcells (CM mode) and as converter of Microcells to Cells (MC mode). The main function of the processor in CM operating mode is that of converting standard ATM cells (53 octets) to a parallel format of microcells (12 or 20 four-bit words, depending on the format programmed) which are processed by a switch, or else, in MC operating mode, the microcells are processed, at the switch output, in reverse manner. It also facilitates functions at ATM level like identifying the virtual path and circuit, performing statistical measurements on throughput to detect loss of information, control quality level of hardware level, insert and extract cells through the external microprocessor which controls the operation of the switch.

Description

PROCESSOR IN ASYNCHRONOUS TRANSFER MODE OF ENTRY AND EXIT TO A SWITCH D E S C R I P C I O N OBJECT OF THE INVENTION The present invention relates to a Processor in Asynchronous Transfer Mode (ATM) interfacing input and output to a switch in an ATM switching matrix, whose main function is to convert standard ATM cells (53 octets) or ATM cells with extended format (56 bytes), to a parallel format of microcells, that is, information packets smaller than an ATM cell, of 12 or 20 four-bit words, depending on the programmed format, which are processed by the switch of packets of an ATM switching matrix, when the processor operates in Cell to Microcell conversion mode (CM operation mode) and convert Micro cells into Cells (MC operation mode) at the output of the switch. It also provides other functions such as statistical flow measurements to detect information loss, hardware quality control, insertion and extraction of cells through the external microprocessor that controls the operation of the commutator.etc.

The present invention has its application within the field of telecommunications and more specifically in systems using switching matrices with asynchronous transfer mode containing packet switches of 12 or 20 four-bit words.

BACKGROUND OF THE INVENTION In the current state of the art several solutions are known to make the switching in Asynchronous Transfer Mode (ATM), all of them with standard ATM cell form The present invention converts ATM cells to a specific intermediate format, called microcells, which will be subsequently treated inde- pendently for their switching, in another integrated circuit capable of working with microcells.

It is essentially composed of three modules, one that converts the ATM cells it receives into microcells (4-bit words), another that converts the micro-cells into cells and a final interface module with the external microprocessor.

The cell converter in microcells also performs statistical measurements of cell flow comparing a series of bits of the ATM header with a cell programmed through the microprocessor, and if they are equal, the cell is counted. It also identifies the circuit and virtual path and inserts parity, cell number, synchronism cell and extracts the routing label from the external memory to insert it into each microcell.

The cell microcell converter also achieves synchronization by means of a synchro-nism algorithm after receiving three frames of correct microcells, detects frame errors by parity calculations, performs statistical measurements of cell flow in the same way as the cell converter to microcells , replaces the microcell header with another for the ATM cell and generates valid cell and cell synchronism signals. The microprocessor interface allows communication with the asynchronous protocol defined for the microprocessors of the Motorola 68xxx family. It also contains the necessary programming and operation control registers of the two previous blocks (CM and MC converter).

BRIEF DESCRIPTION OF THE DRAWINGS Other features and advantages of the invention will become apparent from the detailed description that follows of a preferred embodiment of the invention, taken by way of illustrative and non-limiting example with reference to the accompanying drawings. , in which: Figure 1.1 represents the block diagram of the module responsible for the conversion of ATM cells to micro-cells.

Figure 1.2 represents the internal data structure that flows through the CM module.

Figure 2.1 represents the block diagram of the module responsible for the conversion of microcells to cells.

Figure 2.2 represents the internal data structure that flows through the MC module.

Figure 3 represents the block diagram of the microprocessor interface.

Figure 4 represents the block diagram of the ATM parallel serial converter of the CM converter module (Microcell Cells).

Figure 5 represents the block diagram of the ATM processor and labeling of the CM converter module.

Figure 6 represents the block diagram of the output module of the CM converter.

In Figure 7 the input block of the MC converter module (Cell Microcells) is shown.

Figure 8 shows the ATM processing and tagging block of the MC converter module.

Figure 9 shows the output block of the converter module MC.

DESCRIPTION OF THE PREFERRED EMBODIMENT To carry out the detailed description of the preferred embodiment of the invention, permanent reference will be made to the Figures of the drawings, in which Figure 1.1 shows the block diagram of the module in charge of the conversion of ATM Cells to Microcells. All of its signals are differential, which is why they are physically two signals instead of one. All the signs in this description may not be mentioned.

The block (3) ATM parallel serial converter converts the flow of 53 bytes per standard cell or 56 bytes per extended cell, which enter through an 8-bit input bus (1) in parallel to a flow of 64 bytes per cell that outputs by the bus (4) of output of 64 bits in parallel. This operation allows the reduction of the frequency of the process clock from 311 MHz (2) to 51 MHz (5) allowing the use of CMOS technology. The ATM processor and labeling block (6) executes statistical measurements of ATM cell flow. It also makes the circuit and virtual path identification, generating a 16-bit address (12) for the table implemented in the external memory. It also inserts an extra information field called labeling information, which includes the sequence number, parity of the labeling field, and a 64-bit microprocessor-reserved cell tag, which is intended to detect problems in the the commutator such as loss or deterioration of the information. Also, it inserts control cells from the microprocessor through the connection (13), which are incorporated into the main flow at the appropriate time.

Finally the output block (9) divides the cells, which arrive by the bus (7), from 64 bits by 64 bytes, to 51 MHz (8), in microcells (10) of 4 bits by 12 or 20 words of four bits. This implies that at the output of the processor operating in Cell to Microcell conversion mode (CM mode) we have 16 buses (10.1-10.16) of 4 bits through which the microcells mentioned above exit. There are two formats of possible microcells, 12 or 20 words of 4 bits, so the level of processing in parallel in the switch is programmable, and therefore, the flow ("throughput"). With the format of 20 4-bit words, only microcells are generated by 8 outputs (32 bits in parallel); with the format of 12 4-bit words, microcells are generated by the 16 processor outputs in CM mode. Each bus (10.1-10.16) is associated with its own clock (11.1-11.16) of 68 MHz (plesiochronous system). The routing label obtained from the external memory is added to each microcell. Finally, to obtain a structure of frames in the outputs, each micro-cell flow is inserted a synchronization micro-cell every 1920 bits.

Figure 1.2 shows the format of the data processed internally by the CM module, previously described. Where the data flow of 53 bytes per standard cell or 56 bytes per extended cell, both the information field (1.1) and the 5 header bytes (1.2), enter the block (3) parallel serial converter on the bus ( 1) 8 bits in parallel. And a flow of 64 bytes per cell is obtained by a bus (4) of 64 bits in parallel. This flow contains the information field (4.3) of the cell, 5 bytes of header (4.1) and 3 bytes of padding (4.2) without information, in case the data flow of the bus (1) is 53 bytes per cell. All this information enters the block (6) ATM processing and labeling, and on its exit, by the bus (7), the information flow is obtained that is similar to the one that entered in said block but with an extra information field called labeling information (7.1), which includes the sequence number, parity of the label-do field and a cell tag reserved for the microprocessor, 64 bits, which has the objective of detecting problems in the switch, such as loss or deterioration of the information. After passing through the output block (9) of the CM module, 64-bit by 64-byte cells are obtained, arriving via bus (7), converted into 4-bit microcells (10) by 12 or 20 words of four bits delivered in 16 buses (10.1-10.16) of 4 bits. That is, a microcell format.

Figure 2.1 shows the block diagram of the module in charge of converting Microcells into Cells, it is practically an implementation in reverse of the Cells to Microcells converter block: it executes exactly the inverse function, that is, starting from 16 u 8 (depending on the format of microcells) buses of microcells are extracted ATM standard 53-byte cells, or with extended format of 56 bytes, 8 bits in parallel.

Each input module (16.1-16.16) detects the corresponding micro-dial-wave frame at its input through the buses (14.1-14.16), at 68 MHz (15.1-15.16), and reaches a synchronization state after three corresponding frames. , thus letting the information pass to the following blocks. Frame errors are detected by means of parity calculations. After the data synchronization a cell flow is obtained by the bus (17) of 64 bits in parallel, synchronizing each microcells flow through a FIFO memory by the input from which the data is read, with a only clock (18) at 68 MHz. These cells also contain the aforementioned data field, called labeling information.

The ATM processor and labeling block (19) proves that the parity of the labeling field and the sequence number are correct. It executes the operations related to the identification of the virtual circuit, generating an address (21) that is used to select an ATM header in the external memory that replaces the current one contained in the cell processed by the circuit operating in mode. MC conversion (Microcelu-la-Cell). Furthermore, if the cell being processed is marked as reserved (in the labeling field), then it is extracted by the connection (20) to the microprocessor through a FIFO memory. If it is not extracted, it leaves by a 64-bit data bus (22) with its clock (23) of 68 MHz.

The Emitter Coupling Logic (ECL) output block (24) is essentially a 64-bit 8-bit parallel-serial converter. It also generates valid cell and cell synchronism signals.

Figure 2.2 shows the format of the data processed internally by the MC module, already described previously. In addition, the process is similar to that of Figure 1.2 but in reverse. That is to say, the microcells (14) that enter the MC module by 8 or 16 buses, with identical structure to those of the CM module output, are converted into a 64-byte cell stream, which includes the information field ( 17.4), labeling (17.1), header (17.3) and padding bytes (17.2). This flow is delivered to the ATM processor and labeling block (19) by a 64-bit bus (17) in parallel, and after selecting an ATM header that replaces the current one, it is delivered to the output block (24) by the bus (22), the information field (22.1), header (22.2) and padding bytes (22.3), similar to the bus (17) but without labeling information. The output block of the MC module offers a data flow of 53 bytes, or 56 bytes, including both the information field (25.1) and the header (25.2) by an 8-bit bus (25) in parallel. That is, a cell format.

Figure 3 shows the block diagram of the microprocessor interface, which is capable of communicating with the asynchronous protocol defined for the microprocessors of the Motorola 68xxx family. It contains the necessary registries of programming and control of operation of the modules converters of cells to microcells and vice versa. This interface is shared between the two modules, even physically sharing the aforementioned registers.

The microprocessor interface has the following objectives: The block (27) of synchronous interface is responsible for containing the configuration and status registers of the integrated circuit, the block (28) of asynchronous interface is able to communicate with an interface of a processor of the 68000 family of Motorola, and the multiplexer block (29) is responsible for operating with the CM block when the circuit is programmed in CM mode or with the MC block when the circuit is programmed in MC mode.

The block (28) asynchronous interface is the one that generates all the control signals for the other two blocks of the microprocessor interface. These signals (31) are those necessary to write data in the registers contained in the synchronous block (27) (read or write enabler, data busses and correctly clocked addresses and clock). The block (29) multiple-xor tells you which clock to use: with the CM or MC depending on the mode programmed in the circuit. The inputs (30) are the common inputs of a Motorola bus. In addition, the clock signals also enter and the block has to choose which clock to work with depending on the way in which the circuit is programmed (CM or MC).

The synchronous interface block (27) contains basically the programmable and reading registers associated with the operation of the circuit plus the logic necessary to choose the input and output data, by the bus (33) to be read by the appropriate register or well to get the programmed values correctly. The outputs (32) of this block go to all the entries of the configuration sub-blocks.

The multiplexer block (29) contains multiplexers for routing all the inputs (33) of the CM block or the MC to the other blocks of the microprocessor interface, for the connections (34) and (35), depending on the programming mode . The latter is reflected in an input signal to the block.

Figure 4 represents the block diagram of the converter (3) ATM parallel series of the converter module CM (Cells to Microcells). Technologically, this block is divided into two: one block (36) of Emitter Coupling Logic (ECL), and another block (37) of CMOS technology.

The ECL block (36) receives the 311 MHz ATM data (1) together with its control signals: Valid cell signal (38) and cell synchronization signal (40). Performs a cell integrity check, that is, verifies if the cell has the default length: 53 or 56 bytes. The cell integrity controller block (41) has exactly the same type of signals in its inputs and outputs (42-45), only that its output ensures a correct flow (length and ratio of control / data signals). .

For the parallel serial and cell size conversion to 64 bytes, a CMOS technology FIFO memory (46) and the read (47) and write control (48) control blocks are used. From the read control block, by means of the 64 bit bus (49.1), the cells are stored in the FIFO memory (46) when the write enable connection (49.3) is active. Similarly, when the read enable signal (49.4) is active, the data stored in the memory (46) is transmitted by the 64-bit bus (49.2) to the read control block. Due to the conversion, the speed of the input clock (2) at 51 MHz (5) is reduced by means of a block (50) divisor by six.

Figure 5 represents the block diagram of the ATM processor (6) and labeling of the CM converter module whose functions are those described below: To perform the insertion of a cell through the interface with the external microprocessor, it writes the bytes in a register from which the information is taken (13) and is written into a memory (51) FIFO asyn-chronus. When the microprocessor has finished, an available cell signal (52) is sent to the cell inserter block (53), which inserts said cell into the information flow (4) when there is a gap available and sends it to the memory (57) through the connection (70).

In the extraction of the external memory address to fetch a routing label in the external memory, a bus (55) with the values of the bit-pair selecters arrives to the address extractor block (54), called BPSO up to BPS7 and each one is composed of 4 bits. These inputs -come from the microprocessor interface and their function is to select from the header of the ATM cell that is processing within the circuit the bits necessary to compose the necessary address to extract the routing label from an external memory. corresponding to the ATM cell.

The 32-bit statistical counter and the external memory handling (writing and reading) are included in the ATM processor (56). Therefore, it extracts the routing tag. It also performs the reserved cell identification by marking a bit in the labeling field. The function of the ATM processor is to obtain the routing label and insert it into each of the microcells. Its signals are: the data (60) of the memory where the routing labels are stored, the address output (61) that selects in the external memory the ATM header that we want to process, the address entry (62) generated by the block (54) cell address extractor from the bit pairs selectors (BPS), which arrive by the bus (55), the output (63) of the statistical counter of the cells and the signals that go to the memory external to control it: enabler (64) of the output, control (65) of the script, enabler (66) of chip and bus (67) of data. In addition to the output (68) of data that contains the routing label read from the external memory.

The FIFO data memory (57) is used as a non-timer since the frequency that is handled at the output of the CM module is 68 MHz. The same is true for the FIFO memory of the routing label since it is needed only one for each cell. In the FIFOS, interfoliation is made due to the maximum frequency that the FIFOS can handle: 40 MHz. At the output of the memories, the data (7) coming from the cell inserter (53) and the routing label (69) are obtained. I lie.

Figure 6 represents the block diagram of the output module (9) of the CM converter, which is responsible for creating in the generator (59) flows (10.1-10.16) of micro-cells in the outputs: 8 outputs for the format of 20 4-bit words and 16 outputs for the 12-bit 4-bit format. Inserts in each of the flows the routing label (69) and the synchronous microcell to compose frames every 1920 bits. In the labeling processing block (71), the sequence number and parity are calculated, which are inserted in the cell flow, which enters through the bus (7), in the correct position. The synchronization signals (92) and (93) indicate to the block (71) the instant in which the labeling processing is to be performed.

Figure 7 shows the input block of the MC converter module (from Microcells to Cells) containing 16 identical sub-blocks (16.1-16.16). Each of these handles its own clock (15) input.

Depending on the microcell format that is programmed, 8 or 16 sub-blocks will be active, that is, for the format of 20 4-bit words only 8 sub-blocks are used, while for the 12-bit 4-bit word they are used. the 16 are used: flow and bit control in parallel.

The state machine (72) is responsible for the synchronization algorithm in which errors in the data transmission (14) are detected by checking a word (73) of synchronism (parity and key word). The two microcell formats are recognized.

The parity tester (74) calculates the parity bit by bit (sum and module 4) of the frame that is being transmitted at each moment, comparing the result at the end of the frame with the value that is included in the synchronization micro-cell transmitted in the data by the bus (75). If there is an error, the data is considered invalid.

The memory (76) compensates for possible differences in the frequency of the input clocks (15). The data, which arrives on the bus (78), of the 16/8 input memories are read simultaneously with a single clock (77). Therefore it could be said that these memories behave as one that would consist of 16/8 entries for a single 64-bit output. Clock delays that can reach up to 2 cycles are supported.

The output data of the input block (16) consists of a single 64-bit data bus (17) with its own clock (18) through which ATM cells flow with the labeling information.

In Figure 8, which shows the block (19) of ATM processing and tagging of the converter module MC, in the tagging processing block (80), whose inputs are the data bus (17) and its corresponding clock (18), the parity of the labeling is checked and if there is an error the cell is discarded. At the output of this block, the data and its clock are routed, by bus (79) and connection (91) respectively, to the ATM header block.

In the identifier block (81) of the ATM header, a process equivalent to that done in the CM is performed. The only difference with the process in CM lies in the fact that the 16-bit address that is generated from said identification by the selectors (83) of bit pairs, is used to access the bus (21) to a pair of external memories where ATM headers are stored. By programming the circuit will use these headers (88) to modify or replace the headers of the transmitted cells. The data, by the bus (97), and its clock (98) are routed to the next block (82).

In the cell extraction block (82) those cells whose flag in the extraction labeling field is active, are extracted from the data stream and stored in a FIFO memory. These cells can be extracted by the microprocessor byte by byte.

Figure 9 shows the output block (24) of the converter module MC, which makes a serial parallel conversion of the 64-bit stream in parallel, by the bus (22), with a clock (23) of 68 MHz to an 8-bit stream in parallel, through the bus (25), to the output with a clock (26) of 311 MHz (same format as the input of the CM converter module). It is divided into 4 blocks: a pair of memories (85) and (84) FIFO for data, bus (22), and header, bus (88), whose outputs (94) and (95) are routed to a multiplexer (86), which offers a single output (96) to a serial parallel converter (87) made in ECL technology (Emission Coupling Logic) with an input (90) with the output clock at 311 MHz. The connection (89) of header selection indicates if we insert the new header or if we leave the one that already has.

It is not considered necessary to broaden the content of this description so that a person skilled in the art can understand its scope and the advantages derived from the invention, as well as develop and carry out the object of the invention.

However, it should be understood that the invention has been described according to a preferred embodiment thereof, so that it may be susceptible to modifications without implying any alteration of the operation of said invention, being able to affect such modifications, in particular, to the shape, size and / or manufacturing materials.

Claims (8)

NOVELTY OF THE INVENTION CLAIMS

1. - Processor in Asynchronous Transfer Mode (ATM) input and output interface to an ATM switch that converts cells into microcells and vice versa, which is characterized in that its basic structure consists of two converter blocks, one of ATM Cells to Microcelu-las (CM) and another of Cell Microcells (MC), and of an interface with the microprocessor, wherein said converter block (CM) comprises a converter (3) parallel series ATM, a processor (6) ATM and labeling and an output block (9); wherein said converter block (MC) comprises 1 input block (16), an ATM and tagging processor (19) and an output block (24), and wherein said interface with the microprocessor is capable of communicating with the asynchronous protocol defined for the microprocessors of the 68xxx family of Motorola, and is composed of a block (28) of asynchronous interface, a block (27) of synchronous interface and a multiplexer (29).

2. - Processor in asynchronous transfer mode of input and output to an ATM switch, according to claim 1, characterized in that the parallel series ATM converter (3) receives the data in the format of cells of 53 or 56 bytes at 311 MHz, checks the integrity of each cell and converts it into a flow of 64 bytes at 51 MHz using a FIFO memory and read / write control blocks.

3. - Processor in asynchronous transfer mode of input and output to an ATM switch, according to claim 1, characterized in that the labeling and ATM processor (6) inserts cells through the interface with the external microprocessor in the flow of information, extracts the routing label and incorporates a new labeling field, stored in an external memory, and through FIFO memories it synchronizes the frequencies of the data flow with that of the output block.

4. - Processor in asynchronous transfer mode of input and output to an ATM switch, according to claim 1, characterized in that the output block (9) processes the labeling field to calculate the sequence number and parity which is insert in the flow of cells in the correct position and generate micro-cell flows in the outputs, inserting in each of them the routing label and the synchronization micro-cell to compose frames every 1920 bits.

5. - Processor in asynchronous transfer mode of input and output to an ATM switch, according to claim 1, characterized in that the input block is composed of 16 identical sub-blocks (16.1-16.16), each of which It is responsible for detecting errors in the transmission of data by means of checking a synchronization word, checking the parity to know if the data is valid, compensating for possible differences in the frequency of the clocks of the input data and to get to the output a 64-bit data bus through which ATM cells flow with the labeling information.

6. - Processor in asynchronous transfer mode of input and output to an ATM switch, according to claim 1, characterized in that the labeling and ATM processor (19) is responsible for checking the parity of the labeling and if the cell is erroneous it is discarded, besides extracting from the data flow those cells whose extraction flag of the labeling field is active and storing them in a FIFO memory for subsequent extraction by the microprocessor, and extracting from the received ATM cells in parallel the labeling.

7. - Processor in asynchronous transfer mode of input and output to an ATM switch, according to claim 1, characterized in that the output block (24) performs serial 64-bit parallel conversion in parallel to the 8-bit input in parallel to the output by means of two memories, one for the data and another for the headend, a multiplexer and an ECL technology converter (Emission Coupling Logic) from parallel to serial.

8. - Processor in asynchronous transfer mode of input and output to an ATM switch, according to claim 1, characterized in that the asynchronous interface block (28) generates all the control signals of the synchronous interface block (27) and of the multiplexer (29), which contain, respectively, the programmable and reading registers associated with the operation of the processor and the multiplexers to route all the inputs of the CM or MC converter, according to the programming mode, to the rest blocks of the microprocessor interface.