MXPA00005150A - Scan velocity modulation circuit with multi-mode operation - Google Patents

Abstract

A video display deflection circuit includes a source of a video signal (Y) for displaying picture information contained in the video signal in a screen of a cathode ray tube. The video signal provides selectively on-screen-display information and non-on-screen-display information. A source of a first control signal (OSD_FLAG) has a first value, when the video signal provides on-screen-display information and a second value, when said video signal provides non- on-screen-display information. A waveform generator (63) is responsive to the first control signal for generating a second signal (63b) at a frequency that is related to a deflection frequency having a first waveform, when the video signal provides on-screen-display information, and a second waveform, that is different from the first waveform, when the video signal provides non- on-screen-display information. A modulator (31) generates a modulated correction signal (31b) by modulating, in accordance with the second signal, a time-derivative signal (30a) produced from the video signal. The correction signal is coupled to a scan velocity modulation winding (L1) to produce scan velocity modulated deflection of the electron beam.

Description

EXPLORING SPEED MODULATION CIRCUIT WITH MULTIPLE MODE OPERATION The invention relates to adjusting beam scanning speed to improve sharpness in a frame scan display such as a cathode ray tube (CRT) display. BACKGROUND The sharpness of a video display can be improved by varying the horizontal scanning speed of the beam in response to variations in the luminance component of the video signal. The luminance signal is differentiated and the differentiated luminance signal is used to generate a current to activate an auxiliary beam deflection element, for example, a scanning speed modulation (SVM) coil to modify the scanning speed. horizontal to emphasize the contrast between the light and dark areas of the display. For example, in a black-to-white transition on a given horizontal scan line, the beam scan speed increases approaching the transition, making the display relatively darker in the black area of the transition. When passing the transition to the white area, the beam speed is reduced so that the beam is fixed relatively longer, making the display relatively brighter. The reverse happens when going from light to dark. The scanning speed modulation coil operates to add or subtract from the horizontal beam deviation magnetic field applied by the main horizontal deflection coils. The deflection angle of the beam is a function of the horizontal velocity scanning current, generally a sawtooth current. The horizontal velocity scanning current causes the beam to sweep through a horizontal weft line in a vertical position determined by a vertical velocity sawtooth current coupled to the vertical deflection coils. The sawtooth scanning activation currents are adjusted to consider the fact that the display screen is substantially flat rather than spherical. A given amount of angular beam deviation produces a smaller linear horizontal displacement of the beam at the center of the flat screen and a larger amount at the edges of the screen, because the screen is relatively farther from the beam source when scanning on the edges of the screen that in the center of the screen. It may be desirable to display, for example, screen display (OSD) characters on the screen of the cathode ray tube. The scanning speed modulation current is commonly optimized for visual content, not screen display. Therefore, when the screen display character is displayed on the screen of the cathode ray tube, the scanning speed modulation current could, inconveniently, even degrade the sharpness of the image for visual content of screen display. In a prior art, circuits are provided to selectively deactivate the normal operation of the scanning speed modulation circuit during the screen display operation. It may be desirable to produce a waveform for the scanning speed modulation current that is optimized for screen display and a different waveform optimized for non-display on the screen and for dynamically selecting the appropriate waveform. The selection can be changed region by region of the cathode ray tube screen, in accordance with the presence or absence of visual display content. In carrying out an aspect of the invention, a signal indicative of the start and end positions of the screen display inserts in corresponding regions of the screen display screen is provided. The waveform used to generate the scanning speed modulation current is dynamically selected, in accordance with the signal indicative of the start and end positions. In this way, optimization can be obtained separately for visual contents of screen display and non-display screen. In carrying out an aspect of the invention, a selection of the waveforms of the scanning rate modulation control signal that is coupled to the modulator is made out of the path of the video signal. As explained above, the scanning speed modulation control signal varies according to the position of the beam. Therefore, conveniently, different scanning speed modulation current waveforms are produced for visual contents of screen display and non-display screen, respectively. Brief Description of the Invention In a configuration showing one aspect of the invention, a video signal selectively provides a first type of visual content and a second type of visual content. When each of the types of visual content is provided, horizontal scanning occurs at a first frequency of deviation. A first control signal has a first value, when the video signal provides the first type of visual content and a second value, when the video signal provides the second type of visual content. A waveform generator responds to the video signal to generate a correction signal coupled to a deflection field in accordance with the video signal to produce modulated deflection of scanning speed of an electron beam. The waveform generator responds to the first control signal to generate a first waveform of the correction signal, when the first control signal is at the first value and a second different waveform, when the first control signal It is in the second value. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates in a block diagram a first portion of a circuit for generating a scanning rate modulation current, including an aspect of the invention.; Figure 2 partially illustrates in block diagram a second portion of the scanning speed modulation current generating circuit, including an aspect of the invention; Figure 3 illustrates a graph to explain the operation of a limiter included in the circuit of Figure 2; and Figure 4 illustrates a graph to explain a waveform generated in the circuit of Figure 1. DESCRIPTION OF THE PREFERRED EMBODIMENT A scanning speed modulation current generating circuit 100 of FIGS. 1 and 2, including aspects of the invention, generates a luminance signal Y of FIG. 2, an image correction or enhancement signal. OF MODU LAT ION OF SPEED I EXPLORATION. Similar symbols and numbers in Figures 1 and 2 indicate similar functions and items. The EXPLORATION SPEED CONTROL signal, produced in a digital-to-analog converter (D / A) 21, is coupled via a low-pass reconstruction filter 23 and a conventional amplifier 24 to a coil or auxiliary deflection winding of scanning speed modulation L1 to generate an ISVM scanning speed modulation current in coil L1 mounted on a cathode ray tube (CRT) 36. In addition to winding L1, a horizontal deflection winding Ly and A vertical deflection winding Lv are mounted on the cathode ray tube 36 so that the three windings produce a deflection field having a horizontal component and a vertical component, in a known manner. An electrostatic-type scanning speed modulation device can be used, instead of coil L1, for an electrostatic-type cathode ray tube. An auxiliary deflection field produced by coil L1 is used to add or subtract from a horizontal deflection field produced by horizontal deflection main coils, not shown. The reconstruction filter 23 filters the high-frequency components of the signal EXPLORATION SPEED MODE LAYOUT OUTPUT produced by the discrete quantization levels in the EXPLORATION SPEED LIGHT MODULE OUTPUT signal. The impedance of the coil L1 produces a significant group delay which can be compensated by introducing an additional delay, not shown, into a video path of a cathode video signal, not shown, of the cathode ray tube 36. This ensures that the video signal reaches the cathode of the cathode ray tube at the same time that the corresponding level of the ISVM modulation current of Figure 2 is developed in the scanning speed modulation coil L1. The luminance or video signal Y of Figure 2 is a digital signal provided as a sequence of words representing brightness or luminance information. The words of the luminance signal Y are updated in synchronization with a clock signal CK1. The signal Y is obtained from a source of multiple standard signals 200. The source 200 selectively generates the Y signal of, for example, an analogue luminance signal component of a baseband television signal, not shown, defined in accordance with a transmission standard, for example, NTSC, using conventional sampling techniques and deployed at a scanning speed of 1 H. The scanning speed of 1 H represents a horizontal speed that is approximately 16KHZ. The source 200 selectively generates the Y signal of an NTSC signal, not shown, which is converted upward at a double scanning speed of 2 H. Additionally, the source 200 selectively generates the Y signal of a high definition or standard definition video signal, not shown, which is defined in accordance with the Advanced Television Systems Committee (ATSC) standard. The source 200 selectively generates the Y signal from a computer graphics video signal, not shown. The Y signal, as well as other digital signals in Figures 1 and 2, can be formatted as a fixed point number. The fixed point number has a fixed number of binary digits or bits and a fixed position for the decimal point with respect to that series of bits. A fixed point number can, for example, be either an unsigned number that is always positive or a complement number of two.

Each fixed point number in Figures 1 and 2 has the following format: < total_bits, int_bits, signature_format > The first article, bits_total, is the total number of bits used to represent the fixed-point value, including integer bits, bit fractions, and signature bit, if any. The second article, int_bits, is the number of integer bits (the number of bits to the left of the binary point, excluding the signature bit, if any). The third article, forma_de_frma, is a letter that specifies the signature format. The letter "u" means an unsigned number and the letter "t" means a complement number of two. In the unsigned format there is no signature bit and, in the complement of two format, the leftmost bit is the signature bit. For example, the fixed point number, 0101 in binary, defined by the < 4.2, t > has the value of 2.5 in decimal. The video signal or luminance Y of Figure 2 is coupled to a digital differentiator formed by a filter stage 20 which operates as a transverse or comb filter, including one aspect of the invention. In the filter stage 20, the signal Y is delayed in a clock delay element 20a by a delay time equal to a single period of the clock signal CK1 to produce a delayed signal 20b. The delayed signal 20b is selectively coupled via a pair of terminals 20c and 20d of a selector switch 26 to an input terminal 27a of a subtracter 27, when an interrupt control signal 28 of the switch 26 of Figure 2 is in a first state. The delayed signal 20b is further delayed in a clock delay element 20e by a delay time equal to the single period of the clock signal CK1 to produce an additional delayed signal 20f. The additional delayed signal 20f is selectively coupled, in place of the signal 20b, via a terminal 20g and the terminal 20d of the selector switch 26 to the input terminal 27a of a subtracter 27, when the interrupt control signal 28 is in a second state. The state of the signal 28 is determined in a decoder stage 66 of Figure 1. The decoder stage 66 sets the state of the signal 28 in accordance with a state of the binary signal DISPLAY INDICATOR ON DISPLAY provided, for example, a microprocessor or a video processor, not shown. The SCREEN DISPLAY INDICATOR signal indicates pixel start and stop positions of the cathode ray tube screen in which a visual content of screen display characters is inserted in conventional manner. The term on-screen display character here also identifies computer graphics or other image scenes having defined edge objects that can be processed with respect to the scanning speed modulation in a manner similar to the way the image processing is processed. visual content of screen display characters. The SCREEN DISPLAY INDICATOR signal is in a state in a region of the cathode ray tube screen, when the displayed pixel of the Y signal contains visual content of screen display characters and in an opposite state in a region of the screen. cathode ray tube screen, when the displayed pixel of the Y signal contains visual content not display on screen. The non-display visual content is a scene commonly obtained with a camera. Whereas, the visual content of screen display is commonly obtained from a character generator included in, for example, a television receiver. The signal Y of Figure 2 is also coupled to an input 27b of the subtracter 27. The subtracter 27 generates a filtered or differentiated signal by subtracting the selected signal at the terminal 27a from that of the terminal 27b. The signal 25, which contains a time derivative, dY / dt information of the luminance signal Y provides information of a variation or brightness transition from light to dark or from dark to light in an image produced by an electron beam in the cathode ray tube 36. The time derivative is obtained in the filter stage 20 by passing in the signal 25 high frequency components and filtering low frequency components of the signal Y. The transfer response of the filter stage 20 is selected, in accordance with the frequency of the clock signal CK1 and the status of the control signal 28. Conveniently, the interrupt control signal 28 is in the first state to select the single delay element 20a in the filter stage 20 , when the signal Y containing the visual content of on-screen display characters is obtained from the high-definition ATSC video signal, not shown, or from the video graphics video signal, not shown. The interrupt control signal 28 is in the second state, selecting both delay elements 20a and 20e in step 20, when the signal Y is obtained from an NTSC video signal, not shown, which contains the non-display visual content. on screen and when the Y signal is obtained from the standard definition ATSC video signal, not shown. However, in another example, depending on the visual content, it may be desirable to have the control signal 28 in the second state, instead, when the Y signal is obtained from the high definition ATSC video signal. The frequency of the clock signal CK1 is selected by the microprocessor, not shown. When the Y signal is obtained from the NTSC video signal, not shown, the frequency of the signal CK1 is 27 Mhz. On the other hand, when the Y signal is obtained from any of the ATSC, the computer graphics and the NTSC video signals, not shown, which are converted upwards for adaptation to display at a scanning speed of 2 H, the frequency of the signal CK1 is 81 Mhz. Consequently, the transfer response of the filter stage 20 for the Y signal, obtained from the NTSC video signal containing visual content of non-display on the screen and displayed at the scanning speed of 1 H, is 6 dB per octave to one frequency of 6.75 Mhz. The transfer response of the filter stage 20 for the non-screen display signal Y obtained from NTSC, converted upward to the scanning speed of the 2 H video signal or the Y signal obtained from the ATSC video signal is 6dB per octave up to a frequency of 13.5 Mhz. The transfer response of the filter stage 20 for the Y signal obtained from an ATSC high definition video signal is 6 dB per octave up to 20.25 Mhz. The filtered high-pass or differential signal 25 is coupled via a conventional scaling step between conventional 2 to generate a signal 29a which is coupled to a limiting stage 30 to generate a signal 30a. As shown in a scan speed modulation transfer curve of Figure 3, the value of the signal 30a varies generally linearly with that of the Y signal of a limit of, for example, plus 219, when the numerical value of the signal Y is positive, to a limit of minus 219, when the numerical value of the signal Y is negative. Similar symbols and numbers in Figures 1, 2 and 3 indicate similar items or functions. These limits are selected to limit a component of the signal 30a, when the signal Y is at a frequency at which the transfer response of the filter stage 20 is at a maximum. At the limit value, the signal 30a produces a maximum scanning speed modulation output. A modulation m ultiplier 31 receives the signal 30 a and a modulation control signal 31 a to generate a signal indicative of the scanning speed modulation level 31 b by multiplication. The signal 31 a is indicative of the position of the beam on the screen of the cathode ray tube 36, as will be described later. The signal 31 b is coupled via a conventional 256 splitter scaling stage 32 to generate a signal indicative of the scanning speed modulation level 22. The signal 22 is coupled to an input of a digital-to-analog converter (D / A) ) 21 that produces the analog signal EXPLORATION SPEED LIGHT MODULE EXIT, as mentioned above, according to the value of each word of the signal 22. Therefore, the signal EXPLORING SPEED LATAM MODE EXIT has discrete quantization levels in accordance with the values of the word sequence of the digital signal 22. Signal 31 a causes the ISVM modulation current of Figure 2 to vary in accordance with the beam spot position on the screen. The control signal 31 a is generated in the portion of the circuit 100 of Figure 1, described below. A register 35 containing a signal 35a provided by the microprocessor, not shown, is representative of the total number of pixels in a given horizontal line of the cathode ray tube. The signal 35a is coupled via a division scaling stage between 2 37 to an input of the subtracter 38. A counter 39 counts at the speed of the clock signal C K1. The counter 39 generates a signal 39a representative of a pixel currently displayed. The signal 35a is coupled to an input of a subtracter 38 and subtracted from it. During the horizontal line, an output signal 38a of the subtracter 38 varies from a positive value, representative of one half of the total number of pixels in the horizontal line, to a negative value, representative of one half of the total number of pixels. The output signal value 38a crosses a value of zero when the electron beam is in the center of the horizontal line. The signal 38a is coupled to an absolute value producing stage 40 which produces a signal 40a that contains the absolute value of the signal 38a. During the horizontal line, the output signal 40a varies from a positive value, representative of one half of the total number of pixels, and reaches the value zero at the center of the horizontal line. Subsequently, the signal 40a varies from zero to the positive value, representative of one half of the total number of pixels. Therefore, the signal 40a is analogous to an analog waveform in triangular form of horizontal velocity having a peak value in the center of the horizontal line. The frequency of the signal 40a is determined in accordance with the scanning speed, for example, 1 H or 2 H. Similarly, a register 55 of Figure 1 containing a signal 55a provided by the microprocessor, not shown, is representative of the total number of horizontal lines in the cathode ray tube frame. The signal 55a is coupled by a division scaling step between 2 57 to an input of a subtracter 58. A line counter 59 generates a signal 59a representative of the horizontal line currently being deployed in the cathode ray tube. The signal 55a is coupled to an input of the subtracter 58 and subtracted therefrom. During a vertical sweep of the cathode ray tube, an output signal 58a of the subtracter 58 varies from a positive value, representative of one half of the total number of lines, to a negative value, representative of one half of the total number of lines. The value of the output signal 58a crosses the zero value when the electron beam is in the vertical center of the frame. The signal 58a is coupled to an absolute value producing stage 60 which produces a signal 60a that contains the absolute value of the signal 58a. During vertical scanning, the output signal 60a varies from a positive value, representative of one half of the total number of lines and reaches the zero value in the vertical center of the frame. Subsequently, the signal 60a varies from zero to a positive value, representative of one half of the total number of lines. Therefore, the signal 60a is analogous to an analog waveform in a vertical velocity triangular shape having a peak value at the center of the vertical scan. When the signal Y is displayed at the scanning speed of 1 H, the values of the signals 35a and 55a are, illustratively, set at 640 and 480, respectively. Otherwise, the values of signals 35a and 55a are illustratively set, in 1920 and 1080, respectively.

The horizontal speed signal 40a and the vertical speed signal 60a are coupled to an adder 61 to produce a sum signal 61 a. The signal 61 a is analogous to an analog waveform of triangular shape of horizontal velocity, which has a peak at the center of the horizontal scan and is placed on an analog waveform in a triangular form of vertical velocity. The triangular-shaped analog waveform has a peak at the center of the vertical scan. The signal 61 a is coupled via a division scaling stage between 16 and 62. The step 62 produces a signal 62 a which is coupled to an input of a slope control multiplier 63. In carrying out an aspect of the invention, a register 64 produces a signal 64a having a value of, for example, 240 provided by the microprocessor, not shown. The signal 64a which provides slope or gain information of the scanning speed modulation control signal 31 is used when the signal Y of FIG. 2 contains visual content of non-display on the screen, a register 65 of FIG. signal 65a having a value of, for example, 120 provided by the microprocessor, not shown. The signal 65a that provides slope or gain control is used when the signal Y in Figure 2 contains visual content of screen display characters. Signal 65a of Figure 1 is coupled via a selector switch71 to an input 63a of multiplier 63, when an interrupt control signal 70 of switch 71 is in a first state. The signal 64a is coupled via the selector switch 71 to the input 63a of the multiplier 63, when the interrupt control signal 70 of the switch 71 is in a second state. Similar to the signal 28, described above, the state of the signal 70 is determined in the decoding stage 66. The decoding stage 66 establishes the state of the signal 70 in accordance with a state of the IN-SCREEN DISPLAY signal. . The interrupt control signal 70 is in the first state, when the Y signal contains visual content of screen display characters, and in the second state, when the Y signal contains visual content of non-display on the screen, the state of the signal 70 varies, in accordance with signal 70, in different regions of the cathode ray tube screen. The multiplier 63 is analogous to an analog amplifier having a variable gain selectively controlled by the parameters contained in the signals 64a and 65a, respectively. The multiplier 63 produces an output signal 63b which is coupled to an input of a subtractor 72 and subtracted there. In carrying out a further aspect of the invention, a register 73 produces a signal 73a having a value of, for example, 20160 provided by the microprocessor, not shown. The signal 73a which provides level offset information is used when the signal Y of FIG. 2 contains visual content of non-display on the screen, a register 74 of FIG. 1 produces a signal 74a having a value of, for example, , 080.

The signal 74a provides level shift control, when the signal Y in Figure 2 contains visual content of screen display characters. The signal 74a of Figure 1 is coupled via a selector switch 75 to an input 72a of the subtractor 72, when the interrupt control signal 7 of the switch 75 is in a first state. The signal 73a is coupled via the selector switch 75 to the input 72a of the subtracter 72, when an interrupt control signal 76 of the switch 75 is in a second state. Similar to the signals 28 and 70, mentioned above, the state of the signal 76 is determined in the decoding stage 66. The decoding stage 66 establishes the state of the signal 76 in accordance with a state of the ON-SCREEN DISPLAY INDICATOR signal. For example, the interrupt control signal 76 may be in a first state, when the signal Y in figure 2 contains visual content of display characters, and in the second state, when the signal Y contains visual content of non-display in screen, the subtracter 72 of Figure 1 produces an output signal 72b and is analogous to a variable analog level shifter selectively controlled by the values of the signals 73a and 74a, respectively. Conveniently, the signal 72b is coupled via a division scaling stage between 8 77 to an input 78b of a conventional upper limiter 78 which produces an output signal 78a. In carrying out an aspect of the invention, a register 79 produces a signal 79a having a value of, for example, 63 provided by the microprocessor, not shown. The signal 79a which provides an upper limit value of the signal 78a is used when the signal Y of Figure 2 contains visual content of non-display on the screen. A register 95 of Figure 1 produces a signal 95a having a value of, for example, 31 provided by the microprocessor, not shown. The signal 95a which provides an upper limit value of the signal 78a is used when the signal Y of Figure 2 contains visual content of screen display characters. The signal 95a of Figure 1 is coupled via a selector switch 96 to an input 78c of the limiter 78, when an interrupt control signal 97 of the switch 96 is in a first state. The signal 79a is coupled via the selector switch 96 to the input 78c of the limiter 78 when the interrupt control signal 97 of the switch 97 is in a second state. Similar to the signal 28, described above, the state of the signal 97 is determined in the decoding stage 66. The decoding stage 66 establishes the state of the signal 97 in accordance with a state of the signal IND ICA DEPLOYMENT RATE UE IN SCREEN. The interrupt control signal 97 is in the first state, when the signal Y in Figure 2 contains visual content of screen display characters, and in the second state, when the signal Y contains visual content of non-display on the screen. The signal 97 can have different states when the electron beam is in different regions of the cathode ray tube screen. When the value of the division signal between 8 72b is smaller than the upper limit value determined by the signal at the terminal 78c of the limiter 78, a change in the signal 72b produces a corresponding change in the signal 78a. On the other hand, when the value of the division signal between 8 72b is equal to or greater than the upper limit value determined by the signal at the terminal 78c of the limiter 78, the value of the signal 78a remains constant at the upper limit. Therefore, limiter 78 is analogous to an analog signal limiting state. The signal 78a is coupled to an input 78b of a conventional lower limiter 81 which produces the gain control signal, modulator 31a, mentioned above. A register 80 generates a signal 80a having a value of, for example, 0. The signal 80a containing a lower limit value is coupled to the limiter 81 to set the lower limit value of the signal 31a. when the value of the signal 78a is greater than the lower limit value determined by the signal 80a, a change in the signal 78a produces a corresponding change in the signal 31a. On the other hand, when the value of the signal 78a is equal to or less than the lower limit value determined by the signal 80a, the value of the signal 31a remains constant at the lower limit. Figure 4 illustrates in a two-dimensional graphical diagram the variations of the value of the signal 31a of Figure 1 as a function of a horizontal position X of Figure 4 and as a function of a vertical position V of the beam point in the face of the cathode ray tube. Similar symbols and numbers in Figures 1, 2, 3 and 4 indicate similar items or functions. In Figure 4, the width of the image for a given size of the cathode ray tube screen is normalized to be in a range of values between 0 and 240 and the height of the image to be in a range of values between 0 and 135, representing an aspect ratio of 4: 3. The value of the signal 31 a varies, in accordance with the X and V coordinates, represented by a two-dimensional surface 34. The surface 34 represents an approximation of a two-dimensional parabola surface. The range of values of the signal 31 a changes in the range that can not exceed the limits, 0 to 64. A flat portion 33 of the surface 34 forms a diamond. The portion 33 illustrates the signal level 31 a, during a portion of the cycle, when the upper limiter 78 of Figure 1 provides limiting operation. In accordance with one aspect of the invention, the limiter 78 causes the value of the signal 78a to remain constant at the upper limit. The remainder of the surface 34 of Figure 4 slides downwardly from the peak portion 33. The minimum value of the signal 31 a can not be less than the lower limit established by the lower limiter 81 of Figure 1. Therefore, the lower limiter 81 sets the minimum value and the upper limiter 78 sets the maximum value of the signal 31 a. The slope of the surface 35 representing the signal 31 a of the outer portion 33 of Figure 4 is controlled by the signal at the terminal 63 a of the multiplier 63. As explained above, the signal 31 a is applied to the modulator or multiplier 31 of Figure 2 to generate the modulation control signal 31a.

Claims (19)

1. REVIVIENDS 1. A video display deflection apparatus comprising: means (Lx, Ly, L1) to produce a deflection field that varies a position of an electron beam on a cathode ray tube screen to form a horizontal lines of a plot; a source (200) of a video (Y) signal to display image information contained in such a video signal on said horizontal lines, such a video signal selectively provides a first type of visual content (display on the screen) and a second type (not screen display) of visual content, so that, when each of the types of visual content is provided, horizontal scanning occurs at a first frequency of horizontal deviation; a source of a first control signal (I N D ICADOR OF DEPLOY EG U ON DISPLAY) having a first value, when such a video signal provides said first type of visual content and a second value when said video signal provides the second type of visual content; and characterized by a waveform generator (31) that responds to such a video signal to generate a correction signal (31 b) coupled to such a deflection field production means to vary such deflection field in accordance with such video signal to produce modulated deviation of scanning speed of such electron beam, said waveform generator responds to said first control signal to generate a first waveform of said correction signal, when said first control signal it is at a first value and a second different waveform, when said first control signal is at said second value.
2. 2. A video display deviation apparatus according to claim 1, further characterized by a source of a second signal (40a) at a frequency related to said horizontal deviation frequency, a source of a third signal (60a) at a frequency related to a vertical deflection frequency and an adder (61) to sum such second and third signals to produce a sum signal (61 a), wherein said correction signal (31 b) is produced from such a sum signal .
3. 3. A video display deviation apparatus according to claim 1, further characterized by a source of a second signal (40a) at a frequency related to said horizontal deviation frequency, a source of a third signal (60a) at a frequency related to a vertical deflection frequency, a multiplier (63) responding to at least one of the aforementioned second and third signals and said first control signal (DISPLIANCE INDICATOR ON DISPLAY) to generate a fourth signal (63b) having a frequency that is determined in accordance with said at least one of said second and third signals and a value that is determined in accordance with said first control signal, wherein said correction signal ( 31 b) occurs from the aforementioned fourth signal.
4. 4. A video display diversion apparatus according to claim 3, further characterized by means (72) responsive to said fourth signal (63b) and to said first control signal (IN SCREEN DISPLAY GEAR IN SCREEN) generating a fifth signal (72b) that varies in accordance with such a fourth signal and that includes a first level offset value (73a), when said first control signal is at said first value, and a second level offset value ( 74a) when said first control signal is at said second value.
5. 5. A video display deflection apparatus according to claim 1, characterized in that said first control signal (INDICATION DEPLOYMENT IC IN SCREEN) is at said first value when said video signal provides a type of display character on visual content screen and at such second value, when the aforementioned video signal provides a kind of non-display character on the visual content screen.
6. 6. A video display deviation apparatus according to claim 1, characterized in that said first control signal (DISPLIANCE INDICATOR IN SCREEN) is at said first value when said electron beam is in a first region of such a screen and said second value, when such electron beam is in a second region of said screen.
7. 7. A video display deflection apparatus according to claim 1, characterized in that said deflection field production means (Lx, Ly, L1) operate selectively in a range of deflection frequencies and wherein said correction signal (31). b) varies according to the frequency of deviation selected.
8. 8. A video display deflection apparatus comprising: means (Lx, Ly, L1) to produce a deflection field that varies a position of an electron beam in a screen of a cathode ray tube; a source (200) of a video signal (Y) for displaying image information contained in such a video signal on said screen of the cathode ray tube; a source of a first control signal (I N DICADORA DE DISPLAY EG U ON SCREEN) having a first value, when such electron beam is in a first region of such between and a second value, when such electron beam is in a second region of such screen; and characterized by a waveform generator (31) that responds to such a video signal to generate a correction signal (31 b) coupled to such a deviation field production means to vary, in accordance therewith, such a field of deflection to provide scanning rate modulation, said waveform generator responds to said first control signal to generate a first waveform of said correction signal, when said first control signal is at a first value and a second waveform different from said correction signal, when said first control signal is at said second value.
9. 9. A video display diversion apparatus according to claim 8, further characterized by a source of a second signal (40a) at a frequency related to said horizontal deviation frequency, a source of a third signal (60a) at a frequency related to a vertical deflection frequency, a multiplier (63) responding to at least one of the aforementioned second and third signals and to said first control signal (IN SCREEN DISPLAY GEAR IN SCREEN) to generate a fourth signal (63b) having a frequency that is determined in accordance with that of at least one of said second and third signals and a value that is determined in accordance with said first control signal, wherein said correction signal (31b) b) occurs from the aforementioned fourth signal.
10. 10. A video display diverting apparatus according to claim 9, further characterized by means responsive to said fourth signal (63b) and said first control signal (IN DISPLAY DISPLAY IN SCREEN) to generate a fifth signal (72b) which varies in accordance with such fourth signal and which includes a first level offset value (73a) when said first control signal is at said first value, and a second level offset value (74a) when such The first control signal is at the aforementioned second value. 1.
11. A video display deflection apparatus according to claim 8, characterized in that said first control signal (IN SCREEN DISPLAY GEAR IN SCREEN) is at such a first value when said video signal provides a type of screen display character of visual content and said second value, when said video signal provides a character type of non-display on visual content screen.
12. 12. A video display deflection apparatus, according to claim 8, characterized in that said correction signal (31 b) provides modulated deflection of scanning speed of such electron beam.
13. 13. A video display deviation apparatus according to claim 8, characterized in that said deviation field production means (Lx, Ly, L1) selectively operate in a range of deviation frequencies and wherein said correction signal (31 b) varies according to the frequency of deviation selected.
14. 14. A video display deflection apparatus, comprising: means (Lx, Ly, L1) to produce a deflection field that varies a position of an electron beam in a screen of a cathode ray tube; a source (200) of a video signal (Y) for displaying image information contained in such a video signal on said screen of such a cathode ray tube; means for generating a first signal (31 a) that varies according to the position of said beam in said screen; a source of a clock signal (CK1); and characterized by means (31) responsive to said video signals, first and second to generate a binary correction signal (31 b) having a sequence of states that vary in accordance with such video signal and first signal, the aforementioned correction signal is coupled to such a deflection field production means to produce modulated deflection of scanning speed of such electron beam.
15. 15. A video display diversion apparatus according to claim 14, characterized in that said means (Lx, Ly, L1) to produce a deflection field operate selectively in a range of deflection frequencies (1 H, 2H) and wherein when a first deviation frequency (1 H) of such deviation field is selected, a corresponding frequency of such clock signal (CK1) is selected and when a second deviation frequency (2H) of such deviation field is selected , a different frequency of such a clock signal is selected in a manner to provide multi-mode operation.
16. 16. A video display diverting apparatus according to claim 14, further characterized by a source of a second control signal (DISPLAY INDICATOR IN DISPLAY) having a first value, when such a video signal provides such a first type of visual content (screen display) and a second value, when such a video signal provides such a second type of visual content (not screen display) said second signal is coupled to such correction signal production means (31) to produce a first sequence of states of said correction signal (31 b), when said second signal has said first value, and a second sequence of states of said correction signal, when said second signal has a second value.
17. 17. A video display diversion apparatus according to claim 16, characterized in that said means for generating the first signal (31 a) responds to said clock signal (CK1) and second signal (INPUT DISPLAY DIGECTOR). E IN DISPLAY) to produce a third sequence of states of said first signal, when the second signal has a first value (screen display) and a fourth sequence of states of said first signal, when said second signal has said second value (no display on screen).
18. 18. A video display diverting apparatus according to claim 19, characterized in that said second signal (IN DISPLAY AND DISPLAY SIGNAL INVERT) is at a first value when said video (Y) signal provides a type of video signal. screen display character of visual content and such a second value, when said video signal provides a character type of non-display on visual content screen.
19. 19. A video display deflection apparatus according to claim 14, characterized in that said correction signal (31 b) is coupled to an auxiliary winding (L1) to produce modulated deflection of scanning speed of such electron beam. SUMMARY OF THE INVENTION \ J A video display deflection circuit includes a source of a video signal for displaying image information contained in the video signal on a cathode ray tube screen. The video signal selectively provides on-screen display information and non-display information on the screen. A source of a first control signal has a first value, when the video signal provides on-screen display information and a second value, when such a video signal provides non-display information on the screen. A waveform generator responds to the first control signal to generate a second signal at a frequency 15 which is related to a deviation frequency having a first waveform, when the video signal provides display information on the screen, and a second waveform, which is different from the first waveform, when the signal of video provides information Without displaying on the screen, a modulator generates a modulated correction signal by modulating, in accordance with the second signal, a signal derived in time produced from the video signal. The correction signal is coupled to a winding speed modulation of 25 scan to produce modulated deviation of V scanning speed of the electron beam.