MXPA00000737A - Frequency synthesizer systems and methods for three-point modulation with a dc response - Google Patents

Abstract

A frequency synthesizer includes a controlled oscillator which is responsive to a frequency control input signal, to generate an output frequency. A programmable frequency divider is responsive to the output frequency and to a divider control input, to divide the output frequency by a first integral ratio or by a second integral ratio in response to the divider control input, to thereby produce a divided signal. A phase comparator is responsive to a reference frequency signal and to the divided signal, to compare the reference frequency signal and to the divided signal, and thereby produce a first error signal. A sigma deltamodulator is responsive to a modulation input to produce the divided control input. A loop filter is responsive to the first error signal, to thereby produce the frequency control input signal. Ripple compensation signals and direct modulation signals may also be provided, to provide three-point modulator for a frequency synthesizer. Analog and digital embodiments may also be provided.

Description

"SYSTEMS AND METHODS SYNTHETIZERS OF FREQUENCY FOR MODULATION OF THREE POINTS WITH A CURRENT RESPONSE DIRECT " FIELD OF THE INVENTION The present invention relates to radio communications, and more particularly to frequency synthesizers for generating radio signals.

BACKGROUND OF THE INVENTION Frequency synthesizer systems and methods are widely used in radio communications to produce accurate discrete frequency steps. Figure 1 illustrates a conventional digital frequency synthesizer. A stable reference frequency source such as a crystal oscillator 10 produces an exact signal frequency Fo which can be divided downwards by any integral TM 'relation up to a lower reference frequency Fo / M, using the reference divider 11. A voltage controlled oscillator (VCO) generates a desired output signal. It is desirable that the output signal be controlled up to a multiple of integer determined 'N' times the frequency of - reference divided downward Fo / M, thus generating a desired frequency N-Fo / M. The frequency of the VCO signal in this manner is divided downwards by a programmable 'N' factor into a programmable or variable divider 15, which must produce the frequency Fo / M if the VCO frequency is N-Fo / M as desired . The comparator or phase and frequency detector 12 compares the VCO frequency divided downwardly from a variable divider 15 with the reference frequency divided downwardly from the reference divider 11 in order to produce an error signal, if the frequency or phase is not same. The error signal is filtered in the filter 13 to remove the oscillation at the Fo / M comparison frequency and is applied to the VCO control input 14 in order to correct its frequency and phase until the frequency of the signal is exactly N-Fo / M. In this way, by programming the variable divider 15 to divide by different N values, using for example control bits N, the generated frequency can be controlled up to any multiple of the Fo / M integer, that is, in discrete Fo / M steps. If it is desired to generate a signal frequency that is controlled in very small steps such as 1 Hz, the conventional synthesizer of Figure 1 divides the - Fo reference frequency down to 1 Hz using a large M value. The phase comparator then compares the 1 Hz frequencies, and the filter works to filter the 1 Hz oscillation, which usually produces prolonged filtration time constants. Consequently, a conventional synthesizer that produces small frequency step sizes is usually also very slow to change the frequency. Typically, the time to switch the frequency is a minimum of 80 cycles of the reference frequency divided downwardly Fo / M, for example 80 seconds in the example of the step size of 1 Hz. A fractional-N synthesizer, such as illustrated in Figure 2, can solve the problem of long frequency shift time by obtaining frequency step sizes that can be a fraction of the phase comparison frequency. Fractional-N synthesizers generate a signal frequency between two discrete frequencies alternating between the two discrete frequencies in a given pattern. Referring now to Figure 2, a reference source (oscillator) 10 and a reference divider 11 produce a reference frequency divided downwardly Fo / M towards the phase detector 12. A variable or programmable divider 25 divides - Descending the frequency of VCO 14 by a programmable N integer, but with the additional installation that the value of N used can be changed from N to N + l, for example, by a signal at a control input of N / N + l . When "split between N + l" is selected, the next output pulse will occur to a later VCO cycle than it would otherwise. In this way, when the desired VCO frequency to be produced is slightly higher than N times Fo / M, the output pulse of the divider 25 is progressively obtained earlier, causing an increased phase error at the output of the phase detector 12. When this cumulative phase error becomes equal to approximately one VCO cycle, it can be readjusted to zero by delaying the next output pulse of divider 25 causing it to divide by N + 1 for a division cycle. The pattern to divide by N a number of times and then divide by N + l to readjust the cumulative phase error is then repeated. Since the average phase error in this way is retained at zero, the average VCO frequency is between N-Fo / M and (N + l) -Fo / M according to the service factor of dividing .. between N's to divide between- (N + l) 's. The instantaneous phase error however comprises a sawtooth-like waveform that rises linearly during the periods of - divide between N until it is abruptly readjusted by a division by - (N + l). It is also possible to divide by N and divide by Nl to produce frequencies between N and Nl times Fo / M, which is equivalent to dividing by N + l as the interdispersive dominant division relationship with individual divisions by N to readjust the phase error cumulative. Division patterns such as N, N, N, (N + l), N, N, N, (N + l) or (N + l), (N + l), (N + l), N, (N + l), (N + l), (N + l), N, or N, N, (Nl), N, N (N-1), N, N, or (Nl), (Nl), (Nl), ( Nl), N, (Nl), (Nl), (Nl), (Nl), N, .. they are also possible. The sawtooth-like phase error waveform will usually produce unwanted VCO sawtooth frequency modulation unless it is compensated or filtered by using long time constants in the filter 13. Since it is desirable to avoid For long time constants, the fractional synthesizer-N usually uses fluctuation compensation instead. The pattern of the divisions between N and N + l can be generated by applying an increment to a fractional accumulator 22, the module that the denominator of the fractional frequency wishes to generate. For example, if it is desirable to generate frequencies such as (N + 0.1) Fo / M, (N + 0.2) Fo / M, (N + 0.3) Fo / M then the accumulator 22 increases the modulus-10. If an increment of 1 is applied to the accumulator input, assuming that it starts at zero, it will increase through the repetition sequence 0,1,2,3,4,5,6,7,8,9,1,2,3,4,5,6,7,8,9,0 ... t carrier carrier with an overflow or outputs of the 'carrier' during the rolling through module-10 from 9 back to zero. The carrier pulses occur every ten increments, and are used to select the division ratio of N + l of the divider 25. The division cycle produced in this way comprises dividing 9 by N's and dividing by N + l, producing a ratio of average division of N + 0.1. Also, if the increment to the accumulator is 2, it will produce the sequence - 0,2,4,6,8,0,2,4,6,8,0,2 ... t t carrier carrier which has a carrier output every five increments. An increase of 3 produces the sequence 0, 3, 6, 9,2,5, 8, 1, 4,7, 0, ... t t t carrier carrier carrier which produces a pattern of 3 carriers every ten; increments, and so on. In this way, the selection of the increment provides a ratio of dividing by N + l's exactly equal to the desired decimal fraction. In addition, the number of compliance with any time is related to the cumulative phase error outside the phase detector 12 before it is reset (with each carrier pulse causing a division cycle between N + l). The compensation waveform of the desired fluctuation can therefore be obtained by converting the contents of the accumulator to digital-to-analog (D to A) using the converter 21 from D to A. The compensation waveform is then graduated at the correct level and subtracted from the error signal of the phase detector in subtraction apparatus 20. It can be shown that the appropriate gradation includes a factor of 1 / N to make the exact compensation for all values of the integral part of the division ratio N. US Patent Number 4,179,670 issued to Kingsbury discloses that a graduation proportional to 1 / N can be obtained by multiplication with the output pulse from the variable divider 25 that occurs every N VCO cycles and therefore has a brand / space ratio proportional to 1 / N. The Kingsbury patent '670 is incorporated herein by reference. U.S. Patent No. 5,180,993 issued to the present inventor, which is also incorporated herein by reference, discloses an alternative method. Instead of graduating the compensation signal downwards by a factor 1 / N, the phase error signal of the phase detector 12 is graduated upward by a factor proportional to N using a phase detector known as a charge pump having a Programmable output current level. The latter has the additional advantage that changes in the bandwidth of the circuit can also be compensated by varying N. Any method can be used in the present invention.

It is also known that frequency modulation can be applied to a frequency synthesizer digitally by feeding the numerical samples of the modulation waveform to the frequency control input of the synthesizer. The control input comprises an input N to the variable divider 25 from the entire frequency part and an increment input dN to the accumulator 22 from the fractional part of the frequency. The sampling rate to represent the modulation waveform is therefore equal to the count cycle regime at the output of the variable divider 25, ie, nominally Fo / M. This modulated-N fractional synthesizer was developed by Cincinnati Electronics Corporation. These synthesizer circuits also used the technique known as two-point modulation, where modulation components too high to be passed to VCO 14 through filter 13 were also applied directly to VCO as analog frequency modulation, deviating from the filter. The advantage of two-point modulation is that the frequency of VCO is changed by direct analog modulation simultaneously with the change of the average division ratio digitally using digital modulation. Therefore, no phase error due to modulation does not occur in the ideal case. Consequently, the characteristics of the frequency response of the closed circuit have only a second order effect on the modulation frequency response. Unfortunately, the modulated two-point synthesizer described above can be relatively complicated since it generally requires both an analog modulation waveform for VCO modulation and a digitized sampled equivalent version of the modulation waveform. The digital waveform is then effectively converted into a first-order sigma-delta representation of the waveform by means of the accumulator 22. The contents of the accumulator 22 then becomes D to A once more in the converter 21 from D to A to produce a waveform of jitter compensation.

COMPENDIUM OF THE INVENTION The frequency synthesizers according to the present invention generate an output frequency using a controlled oscillator, a programmable frequency divider, a phase comparator, a sigma-delta modulator and a filter. The sigma-delta modulator can respond to an analog modulation input in order to avoid the need for a converter from D to A and an A to D converter, with a consequent reduction in complexity. A highly accurate direct current modulated frequency synthesizer can thus be provided. In particular, frequency synthesizers according to the present invention include a voltage or current controlled oscillator that responds to a frequency control input signal to generate an output frequency. A programmable frequency divider responds to the output frequency and to an input of the divider control, to divide the output frequency by a first integral relation or by a second integral relation in response to the output of the divider control, in order to produce a divided signal in this way. A phase comparator responds to a reference frequency signal and to the divided signal to compare the reference frequency signal and a divided signal and thus produce a first error signal. A sigma-delta modulator responds to a modulation input to produce the divider control input. A filter responds to the first error signal, in order to produce the frequency controlled input signal. In accordance with other aspects of the invention, the sigma-delta modulator also produces a jitter compensation signal and the filter also responds to a jitter compensation signal. further, the controlled oscillator can also respond to the modulation output. A direct modulation injector can also be included which responds to the filter and to the modulation input to produce the frequency control signal. A grading apparatus that responds to the jitter compensation signal may also be included. A compensation injector responds to the grading apparatus and to the first error signal to produce a first compensated error signal and to provide the first error signal compensated to the filter. The sigma-delta modulator itself may include a comparator that compares the control input of the divider and the modulation input, in order to produce a second error signal. An error ihtegrador can include to integrate the second error signal and produce an integrated error signal. A sampling / quantizing apparatus can also be included which samples and quantizes the second error control signal to produce the control input of the divider. When this sigma-delta modulator is used, the filter can respond to the first error signal and the integrated error signal. The sigma-delta modulator can respond to an entry of - Continuously variable analog modulation or a digital modulation input. The present invention also includes frequency synthesizers using three-point modulators. In particular, the controlled oscillator generates an output frequency and a programmable frequency divider divides the output frequency by means of a first or second integral ratio to thereby produce a divided signal. A phase comparator responds to a reference signal and the divided signal, to compare the reference frequency signal and the divided signal. A three-point modulator is provided that responds to a modulation signal and that: (1) generates a sampled and quantized approximation of the modulation signal, and provides the sampled and quantized approximation to the frequency divider to control the first or second relation integral; (2) generates a fae error compensation waveform of the modulation signal and combines the phase error compensation waveform and the phase comparator output to produce a control signal; and (3) combining the modulation signal and the first control signal to produce a second control signal that is applied to the controlled oscillator to generate the output frequency. The three-point modulator can include a sigma-delta modulator in analog or digital form. The digital modes of the modulators according to the present invention can modulate a frequency synthesizer with a digital data stream to produce an output signal modulated at a frequency of the carrier. The modulator includes a controlled oscillator, a filter, a phase comparator, and a programmable frequency divider. The modulator also includes an input register that stores a predetermined portion of the digital data stream, a counter and a memory including a first address input that connects to the input register and a second input that connects to the counter. Memory stores predetermined bit sequences. The memory provides at least one bit as a function of the first address input and the second address input to produce a control signal for the programmable frequency divider. The preference control signal comprises a main sigma-delta data stream. The memory may also provide a sigma-delta fluctuation compensation data stream as a function of the first address input and the second address input that is applied to the filter. The memory may also provide a direct modulation sigma-delta data stream as a function of the first address input and the second address input that is applied to the controlled oscillator. The memory may also include a third address entry which is connected to the frequency control bits of the channel. Then the data stream is a function of the first, second and third address entries. Another embodiment of the digital modulators in accordance with the present invention includes a digital waveform generator that is a digital signal processor, responsive to the digital data stream, to generate numerical samples representing the modulated output signal. A digital sigma-delta converter responds to the digital waveform generator to produce a control signal for the programmable frequency divider. The digital sigma-delta converter includes a digital comparator that responds to the digital waveform generator and a digital accumulator that responds to the digital comparator. The digital sigma-delta converter can also produce a jitter compensation signal that is applied to the filter and can also produce a direct compensation signal that is applied to the controlled oscillator. The digital sigma-delta converter can also respond to the control bits of channel frequency. The frequency synthesizers according to the invention therefore comprise a voltage or current controlled oscillator (VCO) to generate a radio frequency signal and a variable divider circuit to divide the frequency of the radio signal from the VCO down to a frequency of phase comparison. The divided signal is compared in a phase comparator with a reference frequency to produce a phase error signal that is filtered through a filter to produce a control voltage or current for the voltage or current controlled oscillator. The invention further comprises a modulation input to a sigma-delta modulation circuit which quantizes the modulation input signal to a stream of binary symbols at a rate synchronized with the divided signal. The binary symbols vary the division ratio of the variable divisor between two adjacent division ratios such as N and N + in order to cause the synthesizer to generate an instantaneous signal frequency between N times the reference frequency and N + l times the frequency reference. The sigma-delta modulators also contain an error integrator that integrates the difference between the input modulation signal and the quantized modulation signal to produce an integrated error signal. The integrated error signal is combined with the phase error signal to suppress the quantization noise. The invention in this way can provide a frequency synthesizer that allows the frequency of the output signal to be continuously modulated by an analog modulation signal between the discrete pitch frequencies of N and N + l times the reference frequency that will be produced. using a conventional synthesizer. The analog modulation signal can also be applied directly to control the oscillator controlled by voltage or current, bypassing the filter to provide an upper limit for the modulation frequency response that is not limited by the filter. The modulation signal may not be provided in analog form but rather as a sequence of digital samples representative of the waveform. The digital samples are converted into an equivalent sigma-delta symbol stream using digital logic, and the sigma-delta current is used to control the variable divider ratio as before. In addition, a digital accumulator within the sigma-delta conversion logic circuit produces a digital version of the - - integrated error signal that is converted from digital to analog and then combined with the phase error signal to suppress quantization noise. The digital samples can also be converted from digital to analog to produce a direct modulation signal, bypassing the filter in order to increase the high modulation frequency response if necessary. Methods for synthesizing and modulating the related frequency can also be provided.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a functional diagram of a conventional frequency synthesizer. Figure 2 is a functional diagram of a conventional fractional-N frequency synthesizer. Figure 3 is a functional diagram of the direct current modulatable synthesizers according to the present invention. Figures 4a-4c are waveform diagrams for the synthesizers of Figure 3. Figure 5 is a diagram of compensation and modulation injection circuits that can be used in relation to Figure 3.

Figure 6 is a functional diagram of the digital data modulators using the query tables in accordance with the present invention. Figure 7 is a functional diagram of the digital data modulators using a real-time sigma-delta converter according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED MODALITIES The present invention will now be described more fully below with reference to the accompanying drawings, in which the preferred embodiments of the invention are shown. This invention, however, can be encompassed in many different forms and the modalities set forth herein should not be construed as limited; rather, these embodiments are provided so that this disclosure is complete and complete and that it fully conveys the scope of the invention to those skilled in the art. Like reference numbers refer to the same elements. Figure 3 is a functional diagram of the direct current modulatable synthesizers according to the present invention. An analog modulation waveform such as a modulation voltage between 0 and Vcc is applied to the sigma-delta modulator (S?) 107 and optionally simultaneously as direct analog frequency modulation to a controlled oscillator such as VCO 104, adding at the outlet of the filter 102 in the addition board 103 which functions as a direct modulation injector. The sigma-delta modulator 107 generates a pattern of control signals N / N + 1 to the variable divider 106, the pattern having a mark / space ratio representative of the instantaneous modulation signal at its input. This is obtained using the integrator 1071 to form the average of the difference between the output control current from the flip-flop 1073 and the input waveform. If on average the brand / output space ratio is too high, the integrator, which has an inherent inversion, will produce an output voltage that drops until the integrated error voltage falls below the analog comparator 1072 threshold, producing a Binary zero at your exit. The ZERO level is transferred as the next clock pulse from the variable divider 106 to the output of the tilter circuit 1073 thus causing the variable divider 106 to be divided by N instead of N + l, reducing the brand ratio / pattern space of N / N + l. Since the modulation signal lies between the level of ZERO (N) and the level of ONE (N + l), the error reverses its sign and the output of integrator 1071 begins to rise until the threshold of comparator 1072 is crossed over. once again producing an output level of ONE (N + l). The cycle then repeats itself. The integrated error waveform of the analog integrator 1071 is a sawtooth-like waveform that is analogous to the waveform of the cumulative sawtooth phase error from the phase detector 100. The two forms of wave are compared in Figures 4a-4c. Figure 4c shows the output of the sigma-delta error integrator 1071 when the input modulation signal is maintained at a value of 1/4 between the lowest level and the highest level. When the jog circuit 1073 is producing a level of zero on its output, this is below the modulation level of 1/4. The error is therefore negative (-0.25) and the output voltage of the integrator is rising. At the sampling time (1), the integrated error is above the threshold of the comparator 1072 and thus a UNO is placed by clock in the tilter circuit 1073, causing the next division cycle to use a division ratio of N + l as shown in Figure 4a. The output of the jog circuit of a level of ONE is now higher than the modulation input of 1/4 so that the error is positive (+0.75) and the output of the integrator is falling to three times the rate at which I was lifting earlier. At the sampling time 2 the integrated error has therefore calmed down below the threshold and a ZERO is placed on the jogger circuit 1073 by clock, restarting the sequence. Three integration cycles of an error of -0.25 are required for the integrated error to rise by the same amount that falls in an integration cycle of an error of +0.75, thus establishing the mark / space ratio of 1 / 4 desired to control the division by N / N + l cycles of the divider 106. Even though the divider 106 is dividing by N, its output pulse falls progressively earlier than the reference frequency pulse applied to the phase detector 100. Stated differently, the reference pulse is progressively made later. The phase detector 100 is assumed to be a so-called load pump that rotates a negative output current of CONNECTION when the output pulse of the variable divider occurs and DISCONNECTS when a reference frequency pulse occurs, or alternatively spins a CONNECT positive output current pulse if the reference pulse occurs first and DISCONNECT when - the output pulse of the variable divider arrives later. In the example of Figures 4a-4c, a negative current pulse is produced that lasts from the instant in which the output pulse from the divider 106 occurs at the instant in which the reference pulse occurs, which, being progressively later during the periods of dividing by N, produces an increased pulse width. The cycle of dividing by - (N + l) then causes a step delay of one VCO cycle towards the output of the variable divider 106 so that once again it is aligned with the reference pulse, and the width of the error pulse decreases to zero before repeating the sequence. The pulse width is raised according to the equivalent continuous curve of Figure 4b. This is the same way as the built-in error of the integrator 1071. The integrated error waveform is therefore an appropriate phase error cancellation waveform and is added in an adder (offset injector) 101 to the output of the phase detector 100 after appropriately graduating by I / N in the graduation apparatus 105 if this graduation method is used. Alternatively, as described in the Background of the Invention section, the incorporated '993 patent technique can be used, whereby the magnitude of the current pulse of the phase detector 100 is graduated upwardly in proportion to N in time of this. By comparing the waveforms of Figures 4b and 4c, it will be seen that a phase error that appears as a pulse width increasing in a sawtooth manner is canceled by the continuous sawtooth waveform of the integrator 1071 of an equal and opposite mean value. This cancels all error components up to a frequency equal to the reference frequency. The components of the higher frequency error can remain. These are usually of less consequence since the filter 102 in any case normally removes the fluctuation of the reference frequency. Improved cancellation of the components of the higher frequency error can be achieved by sampling the output of the integrator 1071 to generate a compensation waveform that occurs as a pulse around the time the output current driver of the detector occurs. phase. In this way, the output pulse of the phase detector error of more or less constant and variable width is canceled by the pulse of the constant width and the variable magnitude of the integrator 1071. The improvement in the cancellation of the components of fluctuation of Higher frequencies are explained in greater detail in the present incorporated '670 of Ki? \ gsbury which was described in the Background section of the invention. It will be appreciated that, when the phase detector generates an error current pulse then the compensation waveform usually must also be a current pulse. The compensation injector 101 in this manner provides a conversion from a voltage output from the integrator 1071 to a proportional current, as necessary. Figure 5 provides more detail on the waveforms of injection compensation and direct modulation before and after the filter, respectively. Since the phase error current pulses as shown in Figure 4b are negative (pull down), the compensation current is positive (i.e., traction up to Vcc). Therefore, the voltage / current converter 111 must be a unipolar current source which produces a current proportional to the control voltage of the integrator 1071. This current source can also be provided with a TRAINING control input that can be used for synchronize the generation of the compensation current with the moment in which the output pulse of the phase detector occurs. The two currents are joined before applying their sum to the filter 102. The filter 102 - provides an integration function by means of capacitor Co of the main integrator which integrates the error current compensated by fluctuation to produce a control voltage of VCO 104. By integrating the error a second order phase interlock circuit is created which must be stabilized by middle of the damping resistance Ro. More details on damping control are provided in U.S. Patent No. 5,095,288 to the present inventor, which is incorporated herein by reference. With the addition of the damping resistor Ro in series in the main integrator capacitor Co, the output current pulse of the phase detector is preferably absorbed in a relatively smaller Cl capacitor to avoid voltage limitation at the detector output 100 of phase. This can occur when the magnitude of the output current pulse times of the phase detector multiplied by the damping resistance Ro is comparable to the available supply voltage Vcc. In addition, capacitor Cl provides more filtering of the error signal that may be insufficient at high frequencies, necessitating the addition of additional components such as Ll and C2, which form a low-pass network structure Pl with Cl.

If direct analog modulation of the VCO is also used to provide two-point modulation, an appropriate fraction of the modulation voltage is applied to the VCO in addition to the control voltage. There are several techniques for doing this, including the use of a second control input for modulation, using for example a second varactor diode. The modulation input should preferably have a constant sensitivity measured in Megahertz per volt. If the normal control input is used, and it does not have a constant sensitivity but rather a frequency-dependent sensitivity (which is controlled by the variable division ratio 'N'), then the level of the modulation signal of preference graduates depending on 'N' to provide a constant level of modulation. The 'N' dependency can be stored as a set of numerical graduation values in a Read Only Memory Query table, for example, whose method, ie the ROM method, has been used by the applicant in a synthesizer of the prior art incorporated into a Marconi radio product known as SCIMITAR-V, and into a radio product Ericsson LM derivative known as STARCOMM. The required grading factor can also be calculated by a microprocessor using the technique disclosed in the co-filed North American Application Serial Number - 2i called "Systems and Methods for Automatic Deviation Setting and Control in Radio Transmitters "to the present inventor which is also incorporated herein by reference When the appropriately graded modulation waveform is to be combined with the VCO control voltage, as shown in Figure 5, preferably it is applied to the VCO control line through an impedance Z 110a having the same impedance characteristics versus frequency as the impedance that the filter 102 provides in the control line, in order to obtain a modulation frequency response This can be achieved by making the impedance Z 110a using a network have the same structure as the filter 102. This complicated network is often not necessary, however, since those that contribute mainly to the control line impedance at frequencies of interest are the capacitor Co and the damping resistance Ro.Therefore, the injection of direct modulation can be carried out through the simplified impedance 110b comprising a graduated and resistance oi'Ro and a capacitor Co / a graduated. This graduation maintains the same time constant as Ro • Co and therefore maintains an essentially flat modulation frequency response. The use of a modulation injection impedance comprising a Serial capacitor Co / has the additional advantage of isolating the VCO control line from the direct current level that may be present in the modulation input. True direct current modulation however is provided due to the digital modulation applied through the sigma-delta modulator 107. Of course, this particularity of true direct current modulation can be used to obtain continuous frequency tuning between the N-values. Fo / M and (N + l) -Fo / M by varying a modulation input voltage through the scale from 0 to Vcc. Continuous tuning is of use when the frequencies to be transmitted or received are not over a regular frame but are arbitrary such as in HF SSB communication or in communications that suffer from frequency error or Doppler shift, as with satellites in a non-geostationary orbit. While the invention can provide simplified modulation of the synthesizer with an analog modulation signal, it can often be simpler to generate an analog modulation signal digitally. U.S. Patent No. 5,095,288 issued to the present inventor describes an improved quadrature modulator using sigma-delta modulation representations of the analog modulation signals I, Q. When the sigma-delta waveforms represent a modulation by the digital data stream, and the digital data stream is pre-modulated by a filter having a finite impulse response of a few data symbols duration, the number of sigma-delta streams that may be needed to represent all possible waveforms that may occur throughout the period of the symbol are limited, and all of this may be precalculated and stored in a memory such as a ROM. Patent number '288 is incorporated herein by reference. Figure 6 shows a combination of a fractional-N synthesizer and a ROM modulator. The data to be modulated in the synthesizer output signal in the form of frequency modulation or phase which are mathematically related is time-controlled through the shift register 121 which stores the last 'L' data symbols on which the modulation waveform through the current symbol period. The 'L' symbols of the shift register 121 are then used as the direction to ROM 120 to select a pre-calculated waveform. A high frequency clock which is a multiple of the data rate is applied to the counter 122 which forms other address bits towards ROM 120 in order to select in sequence the different points in the modulation waveform to be sent from ROM 120. The output from ROM 120 can of course be a sequence of 1-bit or sigma-delta samples which are then used to control the variable divider 106 to divide between N or N + l according to the precalculated pattern. In the case of precalculated sigma-delta modulation, the analog waveform from an error integrator such as 1071 may no longer be available for use as jitter compensation. If necessary, it can therefore be reconstructed. A second sigma-delta current can be precalculated and stored to represent the jitter compensation waveform which, after proper filtering in the filter 123 to remove the high-frequency sigma-delta components, is added to the output of the phase detector. . It is known that the sigma-delta quantizer first error signal can itself be digitized using a second sigma-delta quantizer and that the two sigma-delta currents can be combined to produce a signal representation having a lower quantization noise. This technique is called "cascaded sigma-delta modulators". The form of the technique illustrated in Figure 6, however, use a ROM modulator to obtain the main sigma-delta current and the second sigma-delta current. If a direct analog modulation signal is also needed, it is also reconstructed. It can be reconstructed from the main sigma-delta output by means of an appropriate low-pass filter. Alternatively it can be represented by still a third precalculated sigma-delta current. The advantage of using a third precalculated delta-sigma stream is that it can be precompensated for delay and distortion due to the frequency response of the filter 124. In the simplest case, the third sigma-delta stream can be an advanced version in time and in the main sigma-delta current. This precompensation simplifies the filter 124 since it does not have to be restricted to have a negligible delay and distortion. Figure 7 shows an alternative project that generates a sigma-delta current in real time from a digital data modulation waveform. The data for modulation (i.e., comprising digital symbols such as UNOS and binary ZEROs) is applied to the Digital Signal Processor 200 which generates a sequence of numerical values representative of a frequency modulation waveform. These numerical values can be converted into an analog waveform using the D to A 204 converter, if necessary to obtain a direct analog modulation waveform. The digital samples of DSP 200 also apply to a digital sigma-delta converter as opposed to the analog sigma-delta 107 modulator of Figure 3. The principle, however, is the same. The output delta-sigma current is fed again and subtracted from the input waveform, this time in the digital comparator 201 in order to generate an error signal. The digital error values are now digitally integrated by accumulating them in the accumulator 202. The most significant bit (sign bit) of the accumulator 202 discloses whether the accumulated error is above or below a nominal threshold of zero and thus represents the same signal as the output of the slicer 1072 of Figure 3. Because the output has already been sampled at time, however, the flip-flop circuit 1073 may not be necessary and the sign bit of the accumulator 202 is already the current of the sigma-delta bit required. This is fed back to the input comparator 201 and used to control the division by N or N + 1 of a variable divider. The total digital value of the accumulator 212 is equivalent to the analog integrator output of the integrator 1071. This value can be converted from digital to analog using the converter 203 D to A to provide the desired jitter compensation waveform to be added to the output of a phase detector. In the above description of Figures 6 and 7, it was assumed that only the desired fractional-N modulation required was for modulation. In other words, fractional-N installation is not described as being used also to generate fractional channel frequencies. This need not be the case, however, in Figure 6, ROM 120 may also have address entries corresponding to different fractional channel frequencies between N-Fo / M and (N + l) -Fo / M and may store sigroa-delta currents that represent a combination of modulation and fractional frequency channel offset. Unfortunately, fractional channel off-centerings may not simply be related to the data regime. For example, in the European cellular system known as GSM, the frequency channels are separated by 200 KHz or 13 MHz / 65, while the data rate is 13 MHz / 48. The size of the ROM due to the relative primacy of 48 and 65 may become excessive. This can be solved by using a real-time sigma-delta converter as in Figure 7. Then, it may be sufficient to add a fractional channel off-center value, modulating data, for example, to the input of comparator 201 using as many less significant bits as necessary to obtain channel frequencies having the desired precision. This arrangement of Figure 7 allows the use of a fractional synthesizer -N having a reference frequency Fref = Fo / M that is much greater than the desired channel separation that may result in the elimination of the need for jitter compensation. D to A 203 and direct modulation D to A 204 thus simplifying the simultaneous generation of modulation and de-centering of the channel frequency. Typical preferred embodiments of the invention have been disclosed in the drawings and in the specification and even when specific terms are used they are used in a generic and descriptive sense and not for limitation purposes, the scope of the invention having been noted in the following claims.

Claims (31)

R E I V I N D I C A C I O N S

1. A frequency synthesizer that generates an output frequency, comprising: a controlled oscillator that responds to a frequency control input signal to generate the output frequency, - a programmable frequency divider that responds to the output frequency and to a divider control input for dividing the output frequency by a first integral ratio or by a second integral ratio in response to the divider control input to thereby produce a divided signal; a phase comparator that responds to a reference frequency signal and to the divided signal to compare the reference frequency signal and the divided signal and thus produce a first error signal; a sigma-delta modulator that responds to a modulation input to produce the divider control input; and a filter that responds to the first error signal to thereby produce the frequency control input signal.

2. A frequency synthesizer according to claim 1, wherein the sigma-delta modulator also produces a jitter compensation signal and wherein the filter also responds to the jitter compensation signal.

3. A frequency synthesizer according to claim 1, wherein the controlled oscillator also responds to the modulation output.

4. A frequency synthesizer according to claim 1, further comprising a direct modulation injector responsive to the filter and the modulation input to produce the frequency control signal.

5. A frequency synthesizer according to claim 2, further comprising: a grading apparatus responsive to the jitter compensation signal; and a compensation injector responsive to the grading apparatus and the first error signal, to produce a first compensated error signal and to provide the first error signal compensated to the filter.

6. A frequency synthesizer according to claim 1, wherein the sigma-delta modulator comprises: a comparator that compares the control input of the divider and the modulation input to produce a second error signal; an error integrator that integrates the second error signal to produce an integrated error signal; and a sampling / quantifier device that samples and quantizes the second error signal to produce the divider control input.

7. A frequency synthesizer according to additional claim 6 wherein the filter responds to the first error signal and the integrated error signal.

A frequency synthesizer according to claim 1, wherein the sigma-delta modulator is a digital sigma-delta modulator that responds to a digital modulation input to produce the control input of the divider.

9. A frequency synthesizer according to claim 1, wherein the modulation input is a continuously variable analog modulation input.

10. A frequency synthesizer that generates an output frequency that includes: a controlled oscillator that generates the output frequency; a programmable frequency divider that divides the output frequency by means of a first or second integral relation to thereby produce a divided signal; a phase comparator that responds to a reference signal and to the divided signal to compare the reference frequency signal and the divided signal; and a three-point modulator that responds to a modulation signal and generates a sampled and quantized approximation of the modulation signal and provides the sampled and quantized approximation to the frequency divider to control the first or second integral relationship, which generates a form of phase error compensation wave of the modulation signal and combines the phase error compensation waveform and the phase comparator output to produce a first control signal, which combines the modulation signal and the first signal of control to produce a second control signal that is applied to the controlled oscillator to generate the output frequency.

11. A frequency synthesizer according to claim 10, wherein the three-point modulator comprises a sigma-delta modulator.

12. A frequency synthesizer according to claim 11, wherein the sigma-delta modulator is a digital sigma-delta modulator.

13. A modulator that modulates a frequency synthesizer with a digital data stream to produce an output signal modulated at a frequency of the carrier, the frequency synthesizer includes a controlled oscillator, a filter, a phase comparator and a frequency divider. programmable frequency, the modulator comprises: an input register that stores a predetermined portion of the digital data stream; a counter that increases to a multiple of the regime of the symbol of the digital data stream; and a memory including a first address input that is connected to the input register and a second address input that is connected to the counter, the memory storing predetermined bit sequences; a memory that provides at least one bit as a function of the first address entry and the second address entry to produce a control signal for the programmable frequency divider; where the programmable frequency divider is connected to the counter to time the counter.

14. A modulator according to claim 13, wherein the memory includes a third address input that is connected with channel frequency control bits, at least one bit being a function of the first, second and third address entries.

15. A modulator according to claim 13, wherein the control signal comprises a main sigma-delta data stream.

A modulator according to claim 15, wherein the memory also provides a sigma-delta fluctuation compensation data stream as a function of the first address input and the second address input, and which is applied to the filter .

A modulator according to claim 16, wherein the memory also provides a direct modulation sigma-delta data stream as a function of the first address input and the second address input, and which is applied to the controlled oscillator .

18. A modulator that modulates a frequency synthesizer with a digital data stream to produce an output signal modulated at a frequency of the carrier, the frequency synthesizer includes a controlled oscillator, a filter, a phase comparator and a frequency divider. programmable frequency, the modulator comprises: a digital waveform generator that responds to the digital data stream to generate numerical samples representing the modulation waveform; and a digital sigma-delta converter that responds to the digital waveform generator to produce a control signal for the programmable frequency divider.

19. A modulator according to claim 18, wherein the digital sigma-delta converter comprises a digital comparator that responds to the digital waveform generator, and a digital accumulator that responds to the digital comparator.

20. A modulator according to claim 18, wherein the digital sigma-delta converter also produces a jitter compensation signal that is applied to the filter.

21. A modulator according to claim 20, wherein the digital sigma-delta converter also produces a direct compensation signal that is applied to the controlled oscillator.

22. A modulator according to claim 18, wherein the digital sigma-delta converter also responds to the channel frequency control bits.

23. A frequency synthesizing method for generating an output frequency comprising the steps of: generating the output frequency from a frequency control input signal; divide the output frequency by means of a first integral relation or by a second integral relation in response to a divider control input to thereby produce a divided signal; comparing a reference frequency signal and the divided signal to thereby produce a first error signal; modulator by sigma-delta a modulation input to produce the divider control input; and filtering the first error signal to thereby produce the frequency control input signal.

24. A frequency synthesizing method according to claim 23, wherein the sigma-delta modulation step also produces a jitter compensation signal, and wherein the filtering step comprises the filtering step of the compensation signal. of fluctuation.

25. A frequency synthesizing method according to claim 23, wherein the generating step further comprises the step of generating the output frequency from the modulation output.

26. A frequency synthesizing method according to claim 23, wherein the sigma-delta modulation step comprises the steps of: comparing the control input of the divider and the modulation input to produce a second error signal; integrate the second error signal to produce an integrated error signal; and take samples and quantify the second error signal to produce the divider control signal.

27. A frequency synthesizing method according to claim 23, wherein the modulation input is a continuously variable analog modulation input.

28. A modulation method for a frequency synthesizer that generates an output frequency, the frequency synthesizer comprises a controlled oscillator that generates the output frequency; a programmable frequency divider that divides the output frequency in order to produce a divided signal; and a phase comparator that responds to a reference signal and to the divided signal to compare the reference frequency signal and the divided signal; the modulation method comprises the steps of: generating a sampling and quantized approximation of the modulation signal and providing the approximation sampled and quantized to the frequency divider; generating a phase error compensation waveform of the modulation signal and combining the phase error compensation waveform and the phase comparator output to produce a first control signal, - and combining the modulation signal and the first control signal to produce a second control signal that is applied to the controlled oscillator to generate the output frequency.

29. A modulation method for modulating a frequency synthesizer with a digital data stream to produce an output signal modulated at a frequency of the carrier, the frequency synthesizer includes a controlled oscillator, a filter, a phase comparator and a programmable frequency divider, the modulation method comprises the steps of: 6 generate numerical samples of the digital data stream representing the modulated output signal; And a digital sigma-delta step that converts the numerical samples to produce a control signal for the programmable frequency divider.

30. A modulation method according to claim 29, wherein the digital sigma-delta conversion step further comprises the step of producing a jitter compensation signal that is applied to the filter.

31. A modulation method according to claim 30, wherein the digital sigma-delta conversion step further comprises the step of also producing a direct compensation signal that is applied to the controlled oscillator.