MX9801126A - Controlador de memoria para descodificador tipo mpeg. - Google Patents

Controlador de memoria para descodificador tipo mpeg.

Info

Publication number
MX9801126A
MX9801126A MX9801126A MX9801126A MX9801126A MX 9801126 A MX9801126 A MX 9801126A MX 9801126 A MX9801126 A MX 9801126A MX 9801126 A MX9801126 A MX 9801126A MX 9801126 A MX9801126 A MX 9801126A
Authority
MX
Mexico
Prior art keywords
memory
fifos
picture
cross
pixel blocks
Prior art date
Application number
MX9801126A
Other languages
English (en)
Other versions
MXPA98001126A (es
Inventor
David Andrew Barnes
Original Assignee
Discovision Ass
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Discovision Ass filed Critical Discovision Ass
Publication of MX9801126A publication Critical patent/MX9801126A/es
Publication of MXPA98001126A publication Critical patent/MXPA98001126A/es

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H04N19/426—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements using memory downsizing methods
    • H04N19/427—Display on the fly, e.g. simultaneous writing to and reading from decoding memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Image Input (AREA)
  • Image Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

Un descodificador del tipo MPEG opera en el modo de almacenamiento de cuadro 2.5 y tiene un manejo de memoria eficiente el cual permite que se almacena y exhiba una imagen B mientras simultáneamente se hace uso de una porcion de la memoria de almacenamiento de cuadro. El cuadro de vídeo es tratado como una cuadrícula, que tiene hileras de bloques de 8 x 8 pixeles. Los bloques de pixel se manipulan en tres memorias FIFO las cuales están conectadas transversalmente en un circuito cerrado. En la memoria operan dos procesos de la siguiente manera, (1) un proceso de reconstruccion de vídeo el cual escribe datos en la memoria, y (2) un proceso de exhibicion, el cual tiene acceso a la memoria y escribe el cuadro de vídeo en otra memoria externa, en un formato de barrido. Una de las tres memorias FIFO acopladas de manera transversal se designa para escritura de soporte, y las otras dos para la lectura de datos de barrido entrelazados 2:1. Las dos memorias FIFO utilizadas para la operacion de barrido se asignan a líneas alternadas de la imagen.
MXPA/A/1998/001126A 1997-02-26 1998-02-10 Controlador de memoria para descodificador tipo mpeg MXPA98001126A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB9704027.3A GB9704027D0 (en) 1997-02-26 1997-02-26 Memory manager for mpeg decoder
GB9704027.3 1997-02-26

Publications (2)

Publication Number Publication Date
MX9801126A true MX9801126A (es) 1998-08-30
MXPA98001126A MXPA98001126A (es) 1998-11-12

Family

ID=

Also Published As

Publication number Publication date
JPH10341444A (ja) 1998-12-22
EP0863676A3 (en) 2001-02-07
US6122315A (en) 2000-09-19
EP0863676A2 (en) 1998-09-09
GB9704027D0 (en) 1997-04-16
KR19980071687A (ko) 1998-10-26
ID19967A (id) 1998-08-27
AR011870A1 (es) 2000-09-13
CN1192106A (zh) 1998-09-02
IL123354A0 (en) 1998-09-24
AU5212998A (en) 1998-09-03
SG68019A1 (en) 1999-10-19
CA2205129A1 (en) 1998-08-26

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Legal Events

Date Code Title Description
FA Abandonment or withdrawal