MX9706495A - Una arquitectura de memoria unificada con asignacion dinamica de memoria de graficos. - Google Patents

Una arquitectura de memoria unificada con asignacion dinamica de memoria de graficos.

Info

Publication number
MX9706495A
MX9706495A MX9706495A MX9706495A MX9706495A MX 9706495 A MX9706495 A MX 9706495A MX 9706495 A MX9706495 A MX 9706495A MX 9706495 A MX9706495 A MX 9706495A MX 9706495 A MX9706495 A MX 9706495A
Authority
MX
Mexico
Prior art keywords
memory
computer system
clients
unified
graphics
Prior art date
Application number
MX9706495A
Other languages
English (en)
Other versions
MXPA97006495A (es
Inventor
Michael J K Nielsen
Zahid S Hussain
Original Assignee
Silicon Graphics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Graphics Inc filed Critical Silicon Graphics Inc
Publication of MX9706495A publication Critical patent/MX9706495A/es
Publication of MXPA97006495A publication Critical patent/MXPA97006495A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/125—Frame memory handling using unified memory architecture [UMA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Image Input (AREA)
  • Image Processing (AREA)
  • Digital Computer Display Output (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Generation (AREA)

Abstract

En la presente invencion se describe un sistema de computadora que proporciona la asignacion dinámica de memoria para gráficos. El sistema de computadora incluye un controlador de memoria, una memoria del sistema, unificada, clientes de memoria cada uno que tiene acceso a la memoria del sistema vía el controlador de memoria. Los clientes de memoria pueden incluir una máquina de representacion de gráficos de compresion/expansion de datos, un dispositivo de entrada/salida, un dispositivo posterior de gráficos. El sistema de computadora proporciona acceso de lectura/escritura a la memoria del sistema, unificada, a través del controlador de memoria, para cada uno de los clientes en memoria. Se incluyen elementos físicos de traduccion para la correlacion de direcciones virtuales de las memorias intermedias de pixeles a las ubicaciones de la memoria física en la memoria del sistema, unificada. Las memorias intermedias del sistema, unificada dinámicamente como baldosas de memoria físicamente contigua. Los elementos físicos de traduccion implementan en cada uno de los dispositivos de computadora, que se incluyen como los clientes de memoria en el sistema de computadora, que incluyen principalmente la máquina de representacion.
MXPA/A/1997/006495A 1996-09-13 1997-08-26 Una arquitectura de memoria unificada con asignacion dinamica de memoria de graficos MXPA97006495A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08713779 1996-09-13
US08/713,779 US6104417A (en) 1996-09-13 1996-09-13 Unified memory computer architecture with dynamic graphics memory allocation

Publications (2)

Publication Number Publication Date
MX9706495A true MX9706495A (es) 1998-06-30
MXPA97006495A MXPA97006495A (es) 1998-10-30

Family

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Also Published As

Publication number Publication date
DE69722117T2 (de) 2004-02-05
EP0829820B1 (en) 2003-05-21
EP0829820A2 (en) 1998-03-18
EP0829820A3 (en) 1998-11-18
CA2214868A1 (en) 1998-03-13
DE69722117D1 (de) 2003-07-03
US6104417A (en) 2000-08-15
JPH10247138A (ja) 1998-09-14
CA2214868C (en) 2006-06-06
US20010019331A1 (en) 2001-09-06

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Legal Events

Date Code Title Description
FG Grant or registration
MM Annulment or lapse due to non-payment of fees