MX2020010614A - Reordenamiento de condicionales compuestas para un circuito corto mas rapido. - Google Patents

Reordenamiento de condicionales compuestas para un circuito corto mas rapido.

Info

Publication number
MX2020010614A
MX2020010614A MX2020010614A MX2020010614A MX2020010614A MX 2020010614 A MX2020010614 A MX 2020010614A MX 2020010614 A MX2020010614 A MX 2020010614A MX 2020010614 A MX2020010614 A MX 2020010614A MX 2020010614 A MX2020010614 A MX 2020010614A
Authority
MX
Mexico
Prior art keywords
ordering
conditions
processor
reordering
circuiting
Prior art date
Application number
MX2020010614A
Other languages
English (en)
Inventor
Amit Jayant Sabne
Eric Avi Brumer
Original Assignee
Microsoft Technology Licensing Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microsoft Technology Licensing Llc filed Critical Microsoft Technology Licensing Llc
Publication of MX2020010614A publication Critical patent/MX2020010614A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3604—Software analysis for verifying properties of programs
    • G06F11/3616—Software analysis for verifying properties of programs using software metrics
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/443—Optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/443—Optimisation
    • G06F8/4441—Reducing the execution time required by the program code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/43—Checking; Contextual analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/43—Checking; Contextual analysis
    • G06F8/433—Dependency analysis; Data or control flow analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Devices For Executing Special Programs (AREA)
  • Executing Machine-Instructions (AREA)
  • Stored Programmes (AREA)

Abstract

Se proporciona un dispositivo de cómputo, que incluye un procesador configurado para recibir código fuente en un compilador. El código fuente puede incluir al menos una condicional compuesta que tiene una pluralidad de condiciones. Para cada condición de la pluralidad de condiciones, el código fuente puede incluir además un bloque de código respectivo que incluye instrucciones para evaluar la condición. Para cada ordenamiento de una pluralidad de ordenamientos de la pluralidad de condiciones, el procesador puede determinar si el ordenamiento satisface una o más restricciones de legalidad. Para cada ordenamiento de la pluralidad de ordenamientos que satisfacen dichas una o más restricciones de legalidad, el procesador puede determinar un costo computacional estimado respectivo para ese ordenamiento. El procesador puede reordenar la pluralidad de condiciones para que tenga un ordenamiento que tenga un costo computacional estimado más bajo de la pluralidad de ordenamientos que satisfacen dichas una o más restricciones de legalidad.
MX2020010614A 2018-04-13 2019-03-12 Reordenamiento de condicionales compuestas para un circuito corto mas rapido. MX2020010614A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/953,334 US11334469B2 (en) 2018-04-13 2018-04-13 Compound conditional reordering for faster short-circuiting
PCT/US2019/021719 WO2019199401A1 (en) 2018-04-13 2019-03-12 Compound conditional reordering for faster short-circuiting

Publications (1)

Publication Number Publication Date
MX2020010614A true MX2020010614A (es) 2020-10-20

Family

ID=66102751

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2020010614A MX2020010614A (es) 2018-04-13 2019-03-12 Reordenamiento de condicionales compuestas para un circuito corto mas rapido.

Country Status (13)

Country Link
US (2) US11334469B2 (es)
EP (1) EP3776182B1 (es)
JP (1) JP7403465B2 (es)
KR (1) KR102696696B1 (es)
CN (1) CN111971651A (es)
AU (1) AU2019253162A1 (es)
BR (1) BR112020018280A2 (es)
CA (1) CA3094994A1 (es)
IL (1) IL277945B1 (es)
MX (1) MX2020010614A (es)
PH (1) PH12020551688A1 (es)
SG (1) SG11202008493SA (es)
WO (1) WO2019199401A1 (es)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200167668A1 (en) * 2018-11-27 2020-05-28 Sap Se Dynamic rule execution order

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JPH0736706A (ja) * 1993-07-19 1995-02-07 Matsushita Electric Ind Co Ltd 最適化コンパイラ
JPH0869380A (ja) * 1994-08-29 1996-03-12 Fujitsu Ltd ソースプログラムチェック装置
JP3650649B2 (ja) * 1995-06-16 2005-05-25 松下電器産業株式会社 最適化装置
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JP3851228B2 (ja) 2002-06-14 2006-11-29 松下電器産業株式会社 プロセッサ、プログラム変換装置及びプログラム変換方法、並びにコンピュータプログラム
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US7747992B2 (en) * 2004-08-23 2010-06-29 Intel Corporation Methods and apparatus for creating software basic block layouts
US7716630B2 (en) * 2005-06-27 2010-05-11 Ab Initio Technology Llc Managing parameters for graph-based computations
JP4860240B2 (ja) * 2005-11-11 2012-01-25 パナソニック株式会社 翻訳方法および実行通知命令の埋め込み方法
US7818720B2 (en) * 2006-01-24 2010-10-19 Freescale Semiconductor, Inc. System and method for control logic code reordering based on stochastic execution time information
US8032875B2 (en) * 2006-11-28 2011-10-04 Oracle America, Inc. Method and apparatus for computing user-specified cost metrics in a data space profiler
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US8429635B2 (en) * 2009-10-28 2013-04-23 International Buisness Machines Corporation Controlling compiler optimizations
US8683468B2 (en) * 2011-05-16 2014-03-25 Advanced Micro Devices, Inc. Automatic kernel migration for heterogeneous cores
US8600727B2 (en) * 2011-10-11 2013-12-03 Unisys Corporation Streamlined execution of emulated code using block-based translation mode
CN103999036B (zh) * 2011-12-16 2017-07-14 英特尔公司 在支持事务的计算机体系结构中使用异常进行代码专业化的方法和系统
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US10175964B2 (en) * 2014-09-26 2019-01-08 Microsoft Technology Licensing, Llc Compiler caching for runtime routine redundancy tracking
US10025690B2 (en) * 2016-02-23 2018-07-17 International Business Machines Corporation Method of reordering condition checks
US11093225B2 (en) * 2018-06-28 2021-08-17 Xilinx, Inc. High parallelism computing system and instruction scheduling method thereof

Also Published As

Publication number Publication date
KR102696696B1 (ko) 2024-08-19
SG11202008493SA (en) 2020-10-29
BR112020018280A2 (pt) 2020-12-29
IL277945B1 (en) 2024-07-01
EP3776182A1 (en) 2021-02-17
JP2021521538A (ja) 2021-08-26
EP3776182B1 (en) 2024-04-24
WO2019199401A1 (en) 2019-10-17
JP7403465B2 (ja) 2023-12-22
CN111971651A (zh) 2020-11-20
US11334469B2 (en) 2022-05-17
AU2019253162A1 (en) 2020-10-01
US20190317881A1 (en) 2019-10-17
US20220283927A1 (en) 2022-09-08
IL277945A (en) 2020-11-30
KR20200139698A (ko) 2020-12-14
CA3094994A1 (en) 2019-10-17
PH12020551688A1 (en) 2021-07-19

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