MX2020008661A - Registro de flujos de memoria cache por solicitud a una memoria cache de nivel superior. - Google Patents

Registro de flujos de memoria cache por solicitud a una memoria cache de nivel superior.

Info

Publication number
MX2020008661A
MX2020008661A MX2020008661A MX2020008661A MX2020008661A MX 2020008661 A MX2020008661 A MX 2020008661A MX 2020008661 A MX2020008661 A MX 2020008661A MX 2020008661 A MX2020008661 A MX 2020008661A MX 2020008661 A MX2020008661 A MX 2020008661A
Authority
MX
Mexico
Prior art keywords
cache
logging
layer
logged
line
Prior art date
Application number
MX2020008661A
Other languages
English (en)
Inventor
Jordi Mola
Henry Gabryjelski
Original Assignee
Microsoft Technology Licensing Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/904,072 external-priority patent/US10496537B2/en
Application filed by Microsoft Technology Licensing Llc filed Critical Microsoft Technology Licensing Llc
Publication of MX2020008661A publication Critical patent/MX2020008661A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3636—Software debugging by tracing the execution of the program
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/3476—Data logging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3065—Monitoring arrangements determined by the means or processing involved in reporting the monitored data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/885—Monitoring specific for caches

Abstract

Registro de seguimiento con base en una capa de memoria caché superior que determina cómo registrar un flujo por una capa de memoria caché inferior. Una segunda memoria caché recibe, de una primera memoria caché de capa inferior, una solicitud de registro que hace referencia a una dirección de memoria. La segunda memoria caché determina si tiene una línea de memoria caché para la dirección de memoria. Cuando la línea de memoria caché está presente, la segunda memoria caché o bien reenvía la solicitud a una siguiente capa de memoria caché de registro o provoca que la línea de memoria caché se registre si la segunda memoria caché es la capa de registro más exterior. Cuando la línea de memoria caché no está presente, la segunda memoria caché provoca que la línea de memoria caché se registre cuando la línea de memoria caché no se determina como registrada por la segunda memoria caché, o cuando se determina como registrada por la segunda memoria caché pero no se determina si la primera memoria caché está al tanto de un valor actual de la línea de memoria caché en la segunda memoria caché.
MX2020008661A 2018-02-23 2019-02-14 Registro de flujos de memoria cache por solicitud a una memoria cache de nivel superior. MX2020008661A (es)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/904,072 US10496537B2 (en) 2018-02-23 2018-02-23 Trace recording by logging influxes to a lower-layer cache based on entries in an upper-layer cache
US15/947,699 US10642737B2 (en) 2018-02-23 2018-04-06 Logging cache influxes by request to a higher-level cache
PCT/US2019/017912 WO2019164730A1 (en) 2018-02-23 2019-02-14 Logging cache influxes by request to a higher-level cache

Publications (1)

Publication Number Publication Date
MX2020008661A true MX2020008661A (es) 2020-09-22

Family

ID=65576730

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2020008661A MX2020008661A (es) 2018-02-23 2019-02-14 Registro de flujos de memoria cache por solicitud a una memoria cache de nivel superior.

Country Status (15)

Country Link
US (1) US10642737B2 (es)
EP (1) EP3756099B1 (es)
JP (1) JP7334163B2 (es)
CN (1) CN111742301A (es)
AU (1) AU2019223807B2 (es)
BR (1) BR112020014668A2 (es)
CA (1) CA3088558A1 (es)
ES (1) ES2943508T3 (es)
IL (1) IL276650B2 (es)
MX (1) MX2020008661A (es)
PH (1) PH12020551310A1 (es)
RU (1) RU2764173C1 (es)
SG (1) SG11202007566WA (es)
WO (1) WO2019164730A1 (es)
ZA (1) ZA202004082B (es)

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Also Published As

Publication number Publication date
WO2019164730A1 (en) 2019-08-29
PH12020551310A1 (en) 2021-09-06
AU2019223807B2 (en) 2024-02-15
IL276650B1 (en) 2023-05-01
JP7334163B2 (ja) 2023-08-28
AU2019223807A1 (en) 2020-07-23
JP2021515287A (ja) 2021-06-17
ES2943508T3 (es) 2023-06-13
ZA202004082B (en) 2021-09-29
KR20200123188A (ko) 2020-10-28
RU2764173C1 (ru) 2022-01-13
SG11202007566WA (en) 2020-09-29
EP3756099B1 (en) 2023-03-29
IL276650B2 (en) 2023-09-01
CA3088558A1 (en) 2019-08-29
IL276650A (en) 2020-09-30
US20190266086A1 (en) 2019-08-29
US10642737B2 (en) 2020-05-05
BR112020014668A2 (pt) 2020-12-01
EP3756099A1 (en) 2020-12-30
CN111742301A (zh) 2020-10-02

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