MX2019002555A - Sistema y metodo de interfaz de dispositivo definida por software. - Google Patents

Sistema y metodo de interfaz de dispositivo definida por software.

Info

Publication number
MX2019002555A
MX2019002555A MX2019002555A MX2019002555A MX2019002555A MX 2019002555 A MX2019002555 A MX 2019002555A MX 2019002555 A MX2019002555 A MX 2019002555A MX 2019002555 A MX2019002555 A MX 2019002555A MX 2019002555 A MX2019002555 A MX 2019002555A
Authority
MX
Mexico
Prior art keywords
software
communication
communication protocol
device interface
firmware
Prior art date
Application number
MX2019002555A
Other languages
English (en)
Inventor
Johannes Jacobs Gysbert
Deodat Du Toit Rudi
Original Assignee
Iot Nxt B V
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Iot Nxt B V filed Critical Iot Nxt B V
Publication of MX2019002555A publication Critical patent/MX2019002555A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/105—Program control for peripheral devices where the programme performs an input/output emulation function
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7817—Specially adapted for signal processing, e.g. Harvard architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/82—Protecting input, output or interconnection devices
    • G06F21/85—Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/34—Network arrangements or protocols for supporting network services or applications involving the movement of software or configuration parameters 
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/18—Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/40—Bus coupling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/12—Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Computer And Data Communications (AREA)

Abstract

La invención se refiere a sistema de interfaz de dispositivo definida por software 10, una interfaz de dispositivo definida por software, puerta de enlace y método para definir una interfaz para un dispositivo que utiliza un protocolo de comunicación específico para propósitos de comunicación. El sistema 10 incluye un microprocesador/unidad de procesamiento 12.1, 12.2 con una pluralidad de pines de comunicación y software/firmware. El software/firmware se configura, con base en un protocolo de comunicación específico que se utiliza por un dispositivo particular 30.1-30.4 para propósitos de comunicación, para, en tiempo de ejecución, asignar/seleccionar uno o más de los pines de comunicación para formar un puerto virtual al cual se puede conectar el dispositivo particular 30.1-30.4, tras recibir una instrucción de configuración de un usuario para implementar el protocolo de comunicación específico. El software/firmware se configura además para implementar el protocolo de comunicación específico a través del puerto virtual, para permitir así comunicación entre el microprocesador/unidad de procesamiento 12.1, 12.2 y el dispositivo 30.1-30.4, cuando el dispositivo 30.1-30.4 se conecta a los pines del puerto virtual.
MX2019002555A 2016-09-05 2017-09-05 Sistema y metodo de interfaz de dispositivo definida por software. MX2019002555A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
ZA201606120 2016-09-05
PCT/IB2017/055324 WO2018042402A1 (en) 2016-09-05 2017-09-05 Software-defined device interface system and method

Publications (1)

Publication Number Publication Date
MX2019002555A true MX2019002555A (es) 2019-12-02

Family

ID=61300208

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2019002555A MX2019002555A (es) 2016-09-05 2017-09-05 Sistema y metodo de interfaz de dispositivo definida por software.

Country Status (11)

Country Link
US (1) US10949365B2 (es)
EP (1) EP3507672A4 (es)
JP (1) JP2019530939A (es)
CN (1) CN109906444A (es)
AU (1) AU2017319719B2 (es)
BR (1) BR112019004408A8 (es)
CA (1) CA3043315C (es)
MX (1) MX2019002555A (es)
NZ (1) NZ752277A (es)
WO (1) WO2018042402A1 (es)
ZA (2) ZA201901972B (es)

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Also Published As

Publication number Publication date
CN109906444A (zh) 2019-06-18
CA3043315A1 (en) 2018-03-08
NZ752277A (en) 2023-05-26
US20190213152A1 (en) 2019-07-11
JP2019530939A (ja) 2019-10-24
ZA201901972B (en) 2024-01-31
BR112019004408A8 (pt) 2023-02-14
ZA202306785B (en) 2024-02-28
EP3507672A4 (en) 2020-03-04
WO2018042402A1 (en) 2018-03-08
CA3043315C (en) 2023-07-18
US10949365B2 (en) 2021-03-16
EP3507672A1 (en) 2019-07-10
AU2017319719A1 (en) 2019-05-02
BR112019004408A2 (pt) 2019-08-13
AU2017319719B2 (en) 2022-09-22

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