MX2017011153A - Transmitter and parity permutation method thereof. - Google Patents
Transmitter and parity permutation method thereof.Info
- Publication number
- MX2017011153A MX2017011153A MX2017011153A MX2017011153A MX2017011153A MX 2017011153 A MX2017011153 A MX 2017011153A MX 2017011153 A MX2017011153 A MX 2017011153A MX 2017011153 A MX2017011153 A MX 2017011153A MX 2017011153 A MX2017011153 A MX 2017011153A
- Authority
- MX
- Mexico
- Prior art keywords
- bit groups
- group
- wise
- parity bits
- parity
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/20—Modulator circuits; Transmitter circuits
- H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
- H04L27/2053—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases
- H04L27/206—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases using a pair of orthogonal carriers, e.g. quadrature carriers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
Abstract
A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to group-wise interleave a plurality of bit groups including the parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups at predetermined positions in the bit groups before the group-wise interleaving are positioned serially after the group-wise interleaving and a remainder of the bit groups before the group-wise interleaving are positioned without an order after the group-wise interleaving so that the puncturer selects parity bits included in the some of the bit groups sequentially and selects parity bits included in the remainder of the bit groups without an order.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562127014P | 2015-03-02 | 2015-03-02 | |
| KR1020150137188A KR102426780B1 (en) | 2015-03-02 | 2015-09-27 | Transmitter and parity permutation method thereof |
| PCT/KR2016/002091 WO2016140513A1 (en) | 2015-03-02 | 2016-03-02 | Transmitter and parity permutation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| MX2017011153A true MX2017011153A (en) | 2017-11-09 |
Family
ID=56950313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| MX2017011153A MX2017011153A (en) | 2015-03-02 | 2016-03-02 | Transmitter and parity permutation method thereof. |
Country Status (4)
| Country | Link |
|---|---|
| KR (1) | KR102426780B1 (en) |
| CN (1) | CN107567692B (en) |
| CA (1) | CA2978535C (en) |
| MX (1) | MX2017011153A (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7706455B2 (en) * | 2005-09-26 | 2010-04-27 | Intel Corporation | Multicarrier transmitter for multiple-input multiple-output communication systems and methods for puncturing bits for pilot tones |
| KR101503058B1 (en) * | 2008-02-26 | 2015-03-18 | 삼성전자주식회사 | Apparatus and method for channel encoding and decoding in communication system using low-density parity-check codes |
| CN101807966B (en) * | 2009-02-13 | 2012-12-12 | 瑞昱半导体股份有限公司 | Parity check code decoder and receiving system |
| EP4117210B1 (en) * | 2010-05-11 | 2024-03-20 | Electronics And Telecommunications Research Institute | Method of transmitting downlink channel rank information through physical uplink shared channel |
| KR20150005853A (en) * | 2013-07-05 | 2015-01-15 | 삼성전자주식회사 | transmitter apparatus and signal processing method thereof |
| KR20150005426A (en) * | 2013-07-05 | 2015-01-14 | 삼성전자주식회사 | transmitting apparatus and signal processing method thereof |
-
2015
- 2015-09-27 KR KR1020150137188A patent/KR102426780B1/en active IP Right Grant
-
2016
- 2016-03-02 MX MX2017011153A patent/MX2017011153A/en active IP Right Grant
- 2016-03-02 CA CA2978535A patent/CA2978535C/en active Active
- 2016-03-02 CN CN201680025662.1A patent/CN107567692B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| KR102426780B1 (en) | 2022-07-29 |
| CN107567692A (en) | 2018-01-09 |
| CA2978535A1 (en) | 2016-09-09 |
| CN107567692B (en) | 2020-09-04 |
| CA2978535C (en) | 2023-10-17 |
| KR20160106476A (en) | 2016-09-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FG | Grant or registration |