MX2010005401A - Superficie de diseño de estructura logica. - Google Patents

Superficie de diseño de estructura logica.

Info

Publication number
MX2010005401A
MX2010005401A MX2010005401A MX2010005401A MX2010005401A MX 2010005401 A MX2010005401 A MX 2010005401A MX 2010005401 A MX2010005401 A MX 2010005401A MX 2010005401 A MX2010005401 A MX 2010005401A MX 2010005401 A MX2010005401 A MX 2010005401A
Authority
MX
Mexico
Prior art keywords
displayed
design surface
actions
logical
macros
Prior art date
Application number
MX2010005401A
Other languages
English (en)
Inventor
Timothy E Getsch
Arthur C Leonard
Pavel R Karimov
Michael J Maccormack
Michael Tucker
Original Assignee
Microsoft Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microsoft Corp filed Critical Microsoft Corp
Publication of MX2010005401A publication Critical patent/MX2010005401A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/30—Creation or generation of source code
    • G06F8/38—Creation or generation of source code for implementing user interfaces
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F40/00—Handling natural language data
    • G06F40/10—Text processing
    • G06F40/166—Editing, e.g. inserting or deleting
    • G06F40/174—Form filling; Merging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/30—Creation or generation of source code
    • G06F8/34—Graphical or visual programming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/451—Execution arrangements for user interfaces
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/54—Indexing scheme relating to G06F9/54
    • G06F2209/543—Local
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/54—Indexing scheme relating to G06F9/54
    • G06F2209/548—Queue

Abstract

Se proporcionan modalidades para presentar componentes para diseñar visualmente estructuras o macros lógicos. En una modalidad, un componente de superficie lógica se presenta, el cual puede incluir una superficie de diseño. La superficie de diseño puede utilizarse para presentar datos que forman uno o más macros. La superficie de diseño puede seleccionarse para recibir macro-datos. Los datos recibidos, que representan un diseño macro, entonces pueden presentarse en la superficie de diseño en un dispositivo de presentación. En otra modalidad, los controles para navegar dentro de los componentes de superficie lógica utilizados para diseñar macros pueden presentarse en un dispositivo de presentación. Un componente de superficie lógica que incluye una agrupación jerárquica de macro-acciones puede presentarse. Una o más acciones puede seleccionarse y puede recibirse una instrucción en una interfase visual para mover acciones seleccionadas entre la agrupación jerárquica. En respuesta a recibir la instrucción de movimiento, pueden presentarse las acciones seleccionadas que se movieron.
MX2010005401A 2007-11-26 2008-11-10 Superficie de diseño de estructura logica. MX2010005401A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/944,792 US8397207B2 (en) 2007-11-26 2007-11-26 Logical structure design surface
PCT/US2008/082950 WO2009070433A2 (en) 2007-11-26 2008-11-10 Logical structure design surface

Publications (1)

Publication Number Publication Date
MX2010005401A true MX2010005401A (es) 2010-06-03

Family

ID=40670830

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2010005401A MX2010005401A (es) 2007-11-26 2008-11-10 Superficie de diseño de estructura logica.

Country Status (11)

Country Link
US (1) US8397207B2 (es)
EP (1) EP2225630A4 (es)
JP (1) JP5362736B2 (es)
KR (1) KR101538907B1 (es)
CN (1) CN101874233B (es)
AU (1) AU2008329949B2 (es)
BR (1) BRPI0820382A2 (es)
MX (1) MX2010005401A (es)
MY (1) MY168663A (es)
RU (1) RU2479011C2 (es)
WO (1) WO2009070433A2 (es)

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Also Published As

Publication number Publication date
BRPI0820382A2 (pt) 2015-05-19
AU2008329949A1 (en) 2009-06-04
US20090138845A1 (en) 2009-05-28
US8397207B2 (en) 2013-03-12
EP2225630A2 (en) 2010-09-08
JP2011507057A (ja) 2011-03-03
JP5362736B2 (ja) 2013-12-11
MY168663A (en) 2018-11-29
RU2479011C2 (ru) 2013-04-10
KR20100081351A (ko) 2010-07-14
KR101538907B1 (ko) 2015-07-24
AU2008329949B2 (en) 2012-09-06
WO2009070433A2 (en) 2009-06-04
CN101874233B (zh) 2014-03-19
WO2009070433A3 (en) 2009-10-15
CN101874233A (zh) 2010-10-27
EP2225630A4 (en) 2010-12-15
RU2010121142A (ru) 2011-11-27

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Owner name: MICROSOFT TECHNOLOGY LICENSING, LLC

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