MX2007005861A - Metodo y sistema para intercambiar datos. - Google Patents

Metodo y sistema para intercambiar datos.

Info

Publication number
MX2007005861A
MX2007005861A MX2007005861A MX2007005861A MX2007005861A MX 2007005861 A MX2007005861 A MX 2007005861A MX 2007005861 A MX2007005861 A MX 2007005861A MX 2007005861 A MX2007005861 A MX 2007005861A MX 2007005861 A MX2007005861 A MX 2007005861A
Authority
MX
Mexico
Prior art keywords
data
format
format converter
exchanging data
shared memory
Prior art date
Application number
MX2007005861A
Other languages
English (en)
Inventor
Arthur M Goldberg
Chin P Wong
Charbel Khawand
Jianping Tao
John J Vaglica
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of MX2007005861A publication Critical patent/MX2007005861A/es

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)

Abstract

La invencion se refiere a un metodo (300) y sistema (100) para intercambiar datos en una arquitectura de multiples nucleos que tiene por lo menos una memoria compartida (114); el metodo puede incluir los pasos de solicitar (312) datos en un primer formato de un rango predeterminado de direcciones en la memoria compartida en donde los datos son compartidos entre diferentes procesadores, almacenar (316) los datos solicitados en una memoria cache (118) para ser recuperados por un convertidor de formato (120) e identificar (320) para el convertidor de formato un tipo de datos para los datos; el metodo tambien puede incluir el paso de, con el convertidor de formato, trasladar (322), con base en reglas predeterminadas, los datos a un segundo formato que es nativo a un procesador (110) que procesara los datos.
MX2007005861A 2004-11-16 2005-11-07 Metodo y sistema para intercambiar datos. MX2007005861A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/990,133 US20060106988A1 (en) 2004-11-16 2004-11-16 Method and system for exchanging data
PCT/US2005/040105 WO2006055291A2 (en) 2004-11-16 2005-11-07 Method and system for exchanging data

Publications (1)

Publication Number Publication Date
MX2007005861A true MX2007005861A (es) 2007-07-04

Family

ID=36387782

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2007005861A MX2007005861A (es) 2004-11-16 2005-11-07 Metodo y sistema para intercambiar datos.

Country Status (5)

Country Link
US (1) US20060106988A1 (es)
EP (1) EP1815342A2 (es)
KR (1) KR20070070213A (es)
MX (1) MX2007005861A (es)
WO (1) WO2006055291A2 (es)

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JP4346587B2 (ja) * 2005-07-27 2009-10-21 富士通株式会社 システムシミュレーション方法
US20070150627A1 (en) * 2005-11-22 2007-06-28 Lsi Logic Corporation Endian mapping engine, method of endian mapping and a processing system employing the engine and the method
US7346762B2 (en) * 2006-01-06 2008-03-18 Apple Inc. Replacing instruction and corresponding instructions in a queue according to rules when shared data buffer is accessed
KR100827704B1 (ko) * 2006-11-29 2008-05-07 삼성전자주식회사 포트별 데이터 입출력 단위가 독립적인 경우에도 데이터 호환을 보장하는 멀티패쓰 억세스블 반도체 메모리 장치 및 그에 따른 데이터 호환방법
DE102006061050A1 (de) * 2006-12-22 2008-06-26 Infineon Technologies Ag Datenverarbeitungsvorrichtung mit Multi-Endian-Unterstützung
JP5097973B2 (ja) * 2007-09-06 2012-12-12 株式会社メガチップス データ処理装置
US20100312934A1 (en) * 2009-06-05 2010-12-09 Taiwan Semiconductor Manufacturing Company, Ltd. System and Method for Multi-Protocol Bus Communications
US9497283B2 (en) * 2013-12-13 2016-11-15 Oracle International Corporation System and method for providing data interoperability in a distributed data grid
KR102407917B1 (ko) 2015-11-12 2022-06-10 삼성전자주식회사 멀티 프로세서에 의해 공유되는 메모리를 포함하는 멀티 프로세서 시스템 및 상기 시스템의 동작 방법
KR102011843B1 (ko) * 2018-04-19 2019-08-19 전운배 데이터 조합형식 변환방법, 장치 및 프로그램
CN113220620B (zh) * 2021-05-21 2024-05-07 北京旋极信息技术股份有限公司 一种用于数据流格式转换的系统以及数据流传输系统
US20230251980A1 (en) * 2022-02-10 2023-08-10 Mellanox Technologies, Ltd. Devices, methods, and systems for disaggregated memory resources in a computing environment

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US5928349A (en) * 1995-02-24 1999-07-27 International Business Machines Corporation Mixed-endian computing environment for a conventional bi-endian computer system
US5970236A (en) * 1995-11-14 1999-10-19 Compaq Computer Corporation Circuit for selectively performing data format conversion
US5781923A (en) * 1996-05-28 1998-07-14 Hewlett-Packard Company Adding a field to the cache tag in a computer system to indicate byte ordering
US6412043B1 (en) * 1999-10-01 2002-06-25 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
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US6675279B2 (en) * 2001-10-16 2004-01-06 International Business Machines Corporation Behavioral memory enabled fetch prediction mechanism within a data processing system
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JP4446373B2 (ja) * 2003-03-19 2010-04-07 パナソニック株式会社 プロセッサ、データ共有装置

Also Published As

Publication number Publication date
WO2006055291A2 (en) 2006-05-26
EP1815342A2 (en) 2007-08-08
WO2006055291A3 (en) 2007-06-07
KR20070070213A (ko) 2007-07-03
US20060106988A1 (en) 2006-05-18

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