LU61089A1 - - Google Patents
Info
- Publication number
- LU61089A1 LU61089A1 LU61089DA LU61089A1 LU 61089 A1 LU61089 A1 LU 61089A1 LU 61089D A LU61089D A LU 61089DA LU 61089 A1 LU61089 A1 LU 61089A1
- Authority
- LU
- Luxembourg
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/086—Emitter coupled logic
- H03K19/0866—Stacked emitter coupled logic
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Detection And Correction Of Errors (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19691929144 DE1929144C (de) | 1969-06-09 | Paritätsschaltung in ECL-Technik mit kurzer Laufzeit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| LU61089A1 true LU61089A1 (en:Method) | 1971-07-01 |
Family
ID=5736442
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| LU61089D LU61089A1 (en:Method) | 1969-06-09 | 1970-06-08 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US3649844A (en:Method) |
| BE (1) | BE751683A (en:Method) |
| FR (1) | FR2049916A5 (en:Method) |
| GB (1) | GB1279182A (en:Method) |
| LU (1) | LU61089A1 (en:Method) |
| NL (1) | NL7007842A (en:Method) |
| SE (1) | SE362325B (en:Method) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3906212A (en) * | 1971-08-18 | 1975-09-16 | Siemens Ag | Series-coupled emitter coupled logic (ECL) circuit having a plurality of independently controllable current paths in a lower plane |
| US4049974A (en) * | 1971-08-31 | 1977-09-20 | Texas Instruments Incorporated | Precharge arithmetic logic unit |
| US4311926A (en) * | 1977-08-11 | 1982-01-19 | Gte Laboratories Incorporated | Emitter coupled logic programmable logic arrays |
| US4319148A (en) * | 1979-12-28 | 1982-03-09 | International Business Machines Corp. | High speed 3-way exclusive OR logic circuit |
| US4408134A (en) * | 1981-01-19 | 1983-10-04 | Advanced Micro Devices, Inc. | Unitary exclusive or-and logic circuit |
| EP0068059B1 (fr) | 1981-06-25 | 1985-02-20 | International Business Machines Corporation | Circuit ou exclusif et circuit de vérification de parité l'incorporant |
| US4605871A (en) * | 1984-03-12 | 1986-08-12 | Amdahl Corporation | Inverter function logic gate |
| US4680486A (en) * | 1984-03-12 | 1987-07-14 | Amdahl Corporation | Combinational logic circuits implemented with inverter function logic |
| JPS6145632A (ja) * | 1984-08-09 | 1986-03-05 | Nec Corp | 電流切換型論理回路 |
| ATE49833T1 (de) * | 1984-09-24 | 1990-02-15 | Siemens Ag | Und-gatter fuer ecl-schaltungen. |
| DE3575059D1 (de) * | 1984-09-24 | 1990-02-01 | Siemens Ag | Und-gatter fuer ecl-schaltungen. |
| US4692641A (en) * | 1986-02-13 | 1987-09-08 | Burr-Brown Corporation | Level shifting circuitry for serial-to-parallel converter |
| US4686394A (en) * | 1986-02-25 | 1987-08-11 | Fairchild Semiconductor | ECL circuit with current-splitting network |
| US4792706A (en) * | 1986-12-16 | 1988-12-20 | Texas Instruments Incorporated | ECL gates using diode-clamped loads and Schottky clamped reference bias |
| DE3829164C1 (en:Method) * | 1988-08-27 | 1989-08-10 | Ant Nachrichtentechnik Gmbh, 7150 Backnang, De | |
| JP3095229B2 (ja) * | 1990-08-31 | 2000-10-03 | 株式会社日立製作所 | マイクロプロセッサ及び複合論理回路 |
| CN114887934B (zh) * | 2022-03-31 | 2024-03-22 | 蜂巢能源科技股份有限公司 | 电芯加工生产线 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3040192A (en) * | 1958-07-30 | 1962-06-19 | Ibm | Logic, exclusive-or, and shift register circuits utilizing directly connected cascade transistors in "tree" configuration |
| US3519810A (en) * | 1967-02-14 | 1970-07-07 | Motorola Inc | Logic element (full adder) using transistor tree-like configuration |
| US3508076A (en) * | 1967-04-26 | 1970-04-21 | Rca Corp | Logic circuitry |
-
1970
- 1970-05-29 NL NL7007842A patent/NL7007842A/xx unknown
- 1970-06-01 US US41901A patent/US3649844A/en not_active Expired - Lifetime
- 1970-06-04 FR FR7020530A patent/FR2049916A5/fr not_active Expired
- 1970-06-08 SE SE07895/70A patent/SE362325B/xx unknown
- 1970-06-08 LU LU61089D patent/LU61089A1/xx unknown
- 1970-06-08 GB GB27522/70A patent/GB1279182A/en not_active Expired
- 1970-06-09 BE BE751683D patent/BE751683A/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| US3649844A (en) | 1972-03-14 |
| FR2049916A5 (en:Method) | 1971-03-26 |
| BE751683A (fr) | 1970-12-09 |
| NL7007842A (en:Method) | 1970-12-11 |
| SE362325B (en:Method) | 1973-12-03 |
| DE1929144B2 (de) | 1972-10-12 |
| DE1929144A1 (de) | 1970-12-23 |
| GB1279182A (en) | 1972-06-28 |