LU500939B1 - Enhanced PLL circuit - Google Patents

Enhanced PLL circuit Download PDF

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Publication number
LU500939B1
LU500939B1 LU500939A LU500939A LU500939B1 LU 500939 B1 LU500939 B1 LU 500939B1 LU 500939 A LU500939 A LU 500939A LU 500939 A LU500939 A LU 500939A LU 500939 B1 LU500939 B1 LU 500939B1
Authority
LU
Luxembourg
Prior art keywords
frequency
pll circuit
controlled oscillator
voltage controlled
vco
Prior art date
Application number
LU500939A
Other languages
English (en)
Inventor
Mohammed Iftekhar
Johannes Christoph Scheytt
Original Assignee
Univ Paderborn
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Paderborn filed Critical Univ Paderborn
Priority to LU500939A priority Critical patent/LU500939B1/en
Priority to PCT/EP2022/083987 priority patent/WO2023099639A1/en
Application granted granted Critical
Publication of LU500939B1 publication Critical patent/LU500939B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Claims (5)

Our ref.: UPA 47518 P LU Application No.: NN -1- LU500939 Ansprüche
1. Verbesserte PLL-Schaltung mit einem Phasendetektorteil (PD) und einem Ladungspumpen- und Schleifenfilterteil (CP+LF), wobei die verbesserte PLL-Schaltung ein Steuersignal (Vprop, Vint; Ver) in Richtung eines spannungsgesteuerten Oszillators (VCO) bereitstellt, wobei ein von dem spannungsgesteuerten Oszillator erzeugtes Ausgangssignal in dem Phasendetektor (PD) mit einem Referenzsignal (Din) verglichen wird, um dadurch mindestens ein Signal (UP, DN) bereitzustellen, das eine Abweichung in Richtung des Ladungspumpen- und Schleifenfilterabschnitts (CP+LF) anzeigt, um dadurch das Steuersignal so zu befähigen, dass das von dem spannungsgesteuerten Oszillator (VCO) erzeugte Ausgangssignal eingerastet bleibt, wodurch der Ladungspumpen- und Schleifenfilterabschnitt (CP+LF) mit einer weiteren Offsetstrommodulation (losp, losn) versehen wird, wobei die Frequenz in Bezug auf die Frequenz des vom spannungsgesteuerten Oszillator erzeugten Ausgangssignals niedrig ist.
2. Verbesserte PLL-Schaltung nach Anspruch 1, wobei die Frequenz der Offset- Strommodulation niedriger ist als die Rauschbandbreite der gesamten PLL-Schaltung.
3. Verbesserte PLL-Schaltung nach Anspruch 1 oder 2, wobei die Schaltung eine integrierte Schaltung aufweist.
4. Verbesserte PLL-Schaltung nach einem der vorhergehenden Anspriiche, wobei die Schaltung diskrete Bauteile aufweist.
5. Verbesserte PLL-Schaltung nach einem der vorhergehenden Anspriiche, wobei der Offsetstrom nur vorübergehend bereitgestellt wird.
LU500939A 2021-12-01 2021-12-01 Enhanced PLL circuit LU500939B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
LU500939A LU500939B1 (en) 2021-12-01 2021-12-01 Enhanced PLL circuit
PCT/EP2022/083987 WO2023099639A1 (en) 2021-12-01 2022-12-01 Enhanced pll circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
LU500939A LU500939B1 (en) 2021-12-01 2021-12-01 Enhanced PLL circuit

Publications (1)

Publication Number Publication Date
LU500939B1 true LU500939B1 (en) 2023-06-01

Family

ID=80222328

Family Applications (1)

Application Number Title Priority Date Filing Date
LU500939A LU500939B1 (en) 2021-12-01 2021-12-01 Enhanced PLL circuit

Country Status (2)

Country Link
LU (1) LU500939B1 (de)
WO (1) WO2023099639A1 (de)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030214330A1 (en) * 2002-05-20 2003-11-20 Fujitsu Limited Phase-locked loop circuit
US20040189402A1 (en) * 2003-03-28 2004-09-30 Holtek Semiconductor Inc. Fast frequency locking method and architecture realized by employing adaptive asymmetric charge-pump current mechanism
US20130200922A1 (en) * 2012-02-02 2013-08-08 Mediatek Inc. Phase frequency detector and charge pump for phase lock loop fast-locking
US8963594B2 (en) 2012-05-11 2015-02-24 Realtek Semiconductor Corporation Phase-locked loop circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030214330A1 (en) * 2002-05-20 2003-11-20 Fujitsu Limited Phase-locked loop circuit
US20040189402A1 (en) * 2003-03-28 2004-09-30 Holtek Semiconductor Inc. Fast frequency locking method and architecture realized by employing adaptive asymmetric charge-pump current mechanism
US20130200922A1 (en) * 2012-02-02 2013-08-08 Mediatek Inc. Phase frequency detector and charge pump for phase lock loop fast-locking
US8963594B2 (en) 2012-05-11 2015-02-24 Realtek Semiconductor Corporation Phase-locked loop circuit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ABDUL MAJEED K K ET AL: "Low power PLL with reduced reference spur realized with glitch-free linear PFD and current splitting CP", ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, SPRINGER NEW YORK LLC, US, vol. 93, no. 1, 21 June 2017 (2017-06-21), pages 29 - 39, XP036316911, ISSN: 0925-1030, [retrieved on 20170621], DOI: 10.1007/S10470-017-1013-4 *
DODEL, N.KLAR, H.OTTE, S.: "49th IEEE International Midwest Symposium on Circuits and Systems", vol. 2, 2006, article "A 9.8-10.7 Gb/s Bang-Bang CDR with Automatic Frequency Acquisition Capability", pages: 46 - 49

Also Published As

Publication number Publication date
WO2023099639A1 (en) 2023-06-08

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Effective date: 20230601