KR980012437A - Method for manufacturing a semiconductor integrated circuit having a double-well structure - Google Patents

Abstract

The present invention relates to a method of fabricating a semiconductor integrated circuit having a double-well structure, in which a plurality of masks for the steps of small, well ion implantation, field ion implantation and channel ion implantation are separately used, In order to solve the problem that a complicated process step is required, the ion implantation process can be performed in a batch by using the same mask but different ion implantation energy. That is, the wells, the channel blocking regions and the channel gate regions are formed first by performing the entire ion implantation at the energy of 500 to 700, 100 to 150, and 30 to 50 keV at the upper portion of the field oxide film, Similarly, the second well, the channel stop, and the channel gate region are also collectively formed by ion implantation with different energy. Thus, the photomask step is significantly reduced, and the well drive-in process is not required.

Description

Method for manufacturing a semiconductor integrated circuit having a double-well structure

The present invention relates to a method of manufacturing a semiconductor integrated circuit having a double-well structure, and more particularly, to a method of manufacturing a semiconductor integrated circuit having a double- And a method of fabricating a semiconductor integrated circuit of a double-well structure, which is implemented so as to be able to be executed collectively in one step. In a semiconductor integrated circuit, it is necessary to form four types of transistors on one substrate in order to optimize the operation performance of a circuit, and a process that enables this is a complementary metal oxide semiconductor (CMOS) ) Structure. That is, as the degree of integration of the semiconductor integrated circuit increases, the scale of the device is reduced (scaling down), so that the power consumption of the chip is limited. In order to keep the power consumption within the allowable range, to be. There are two processes in this CMOS structure, N-well and P- (well). As the trend of large scale integrated circuits continues, the single well structure using P-well or N-well is limited . Recently, a P-well for an NMOS (Negative MOS) and an N-well for a PMOS (Positive MOS) are independently formed in a lowly doped epitaxial layer on a substrate which is doped to a very low level, A double-well process using a heavily doped substrate is becoming increasingly popular in order to prevent a latch-up phenomenon. In the conventional CMOS double well process, well implantation, field implantation, and channel implantation process steps are performed by photomasking (ion implantation) ) Ion implantation process, and the respective ion implantation steps were separately classified. Therefore, there has been a problem that complicated process steps are required to be carried out incidentally. For example, an oxide film or a nitride film is first formed on a silicon substrate, a nitride film is etched through photomasking, and an N-well is formed by ion implantation. Then, a field oxide film is formed on the portion where the N-well is formed, the nitride film is removed, and the P-well is formed by ion implantation using the field oxide film as a mask. The energy of the well ion implantation is 100 keV to 150 keV, and the depth of the well formed by ion implantation is approximately 1 탆 to 1.5 탆. When the ion implantation is completed, a double-well is formed by performing a well drive-in process at a high temperature for a long time, for example, at 1150 ° C for 10 hours to 36 hours. The depth of the well after the well drive-in is 4 탆 to 5 탆. After the formation of the well is completed, the oxide layer, the polycrystalline silicon layer, and the nitride layer are formed again, the active region is etched by photomasking, and the photoresist layer is removed. Then, a field oxide film is formed by sequentially performing an N-field photomask, N-field ion implantation, photomask removal, P-field photomask, P-field ion implantation and photomask removal. Then, the channel gate is formed in the order of photomasking, ion implantation, and photomask removal. That is, six photomasking processes are required for six ion implantation processes, and each photomasking process includes the steps of applying, exposing, developing, and removing photoresist. In the well formation step, a drive-in process is also required as described above.

Therefore, an object of the present invention is to simplify the manufacturing process of a semiconductor integrated circuit of a double-well structure by performing the ion implantation process independently performed at various stages as described above at a specific stage.

FIGS. 1 to 5 are process sectional views showing a part of a method of manufacturing a semiconductor integrated circuit of a double-well structure according to an embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

10: silicon substrate (Si substrate) 12: oxide film

14: Polysilicon layer 16: Nitride layer

18: Photo Resist 20: Field Oxide

22: gate oxide film 24, 26: well,

28, 30: Channel stop area 32, 34: Channel gate

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: (1) sequentially stacking an oxide layer, a polycrystalline silicon layer, and a nitride layer on a silicon substrate; (2) The oxide layer, the polycrystalline silicon layer, and the nitride layer are selectively etched, and a field oxide layer is formed on the etched portion. The oxide layer, the polycrystalline silicon layer, and the nitride layer that are not etched are removed, ; (3) a step in which the first well ion implantation, the field ion implantation, and the channel gate ion implantation are performed on the field oxide film and the gate oxide film at different energy levels; (4) a step of applying a photoresist layer to a part of the upper part of the field oxide film and the gate oxide film, and performing a second well ion implantation, a field ion implantation, and a channel gate ion implantation, -Well structure of a semiconductor integrated circuit. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. 1 to 5 are process cross-sectional views illustrating a method of manufacturing a dual-well structure semiconductor integrated circuit according to an embodiment of the present invention. 1, an oxide layer 12, a polycrystalline silicon layer 14, and a nitride layer 16 are sequentially stacked on an upper surface of a silicon substrate 10 (Si substrate). The stacking method is a conventional method. In the case of the oxide film 12, a thermal oxidation method is used. In the case of the polycrystalline silicon layer 12 and the nitride film 14, a deposition method is used. 2, a photoresist 18 is coated on the nitride layer 16, exposed and developed to form a photomask, and the oxide layer 12, the polycrystalline silicon layer 14, the nitride layer 16 Is selectively etched. The portion where the etching is performed is the portion where the field oxide film 20 of FIG. 3 is formed, and the portion where the etching is not performed and the nitride film 16 remains is the active region. When the etching is completed, the photoresist 18 is removed. The application, exposure, development, etching, removal, etc. of the photoresist 18 are performed according to a conventional method, and a description thereof will be omitted. 3, a field oxide layer 20 is formed on the oxide layer 12, the polycrystalline silicon layer 14, and the nitride layer 16 are etched, and the oxide layer 12, the polycrystalline silicon layer 14, the nitride film 16 is removed, and a gate oxide film 22 is formed in the removed portion, that is, the active region. The field oxide film 20 and the gate oxide film 22 are formed in the same manner as in the conventional structure and forming method. The field oxide film 20 and the gate oxide film 22 are about 1.5 탆 thick and about 1000 Å thick, respectively . Referring to FIG. 4, first well ion implantation, field ion implantation, and channel gate ion implantation are performed on the field oxide film 20 and the gate oxide film 22 at different energies, respectively. That is, well ion implantation is performed by a full ion implantation method at an energy of 500 keV to 700 keV, and the depth of the formed well region 24 is 4 탆 to 5 탆. Therefore, the well drive-in process is not necessary. Field ion implantation is also performed by a full ion implantation method at an energy of 100 keV to 150 keV. At this time, a channel stop region 28 (Channel Stop) is formed to a depth of 4000 Å to 5000 Å below the field oxide film 20. Of course, since the entire ion implantation method is employed, field ion implantation is simultaneously performed in the active region, but the characteristics of the semiconductor device are not affected. Therefore, the illustration is omitted in FIG. A channel gate ion implantation is performed by a full ion implantation method at an energy of 30 keV to 50 keV and a channel gate 32 (channel gate) is formed to a depth of 1000 to 1500 Å under the gate oxide film 22. At this time, since the energy of the ion implantation is not sufficient to penetrate the field oxide film 20 in the field oxide film 20, it is not influenced by the channel gate ion implantation. 5, when the primary ion implantation is completed as described above, a photoresist layer 18 is applied to a portion of the top portion of the field oxide layer 20 and the gate oxide layer 22, Ion implantation, and channel gate ion implantation are performed at different energies. That is, the second well ion implantation is performed at an energy of 500 keV to 700 keV using the photoresist layer 18 as a mask, and the well region 26 is formed to a depth of 4 탆 to 5 탆 as in the first order described above . Secondary field ion implantation is performed using the same photomask as the well ion implantation with an energy of 100 keV to 500 keV. Also, the channel blocking region 30, which is the same as the first order, is formed to a depth of 4000 to 5000 Å from immediately below the field oxide film 20. Secondary channel gate ion implantation is performed using the same photomask at an energy of 30 keV to 50 keV and a channel gate 34 is formed to a depth of 1000 to 1500 Å below the gate oxide film 22. If the P-well, N-field, and N-channel gates are formed by the primary ion implantation of the well, field, and channel gates, the N-well, P- A channel gate is formed, and conversely, an N-well or the like may be formed in the first ion implantation and a P-well or the like may be formed in the second ion implantation.

As described above, conventionally, each of six photomasking processes and accompanying steps are required. However, according to the method of the present invention, instead of reducing the number of photomasking processes by two, So that ion implantation is possible in a batch. In addition, since high-energy ion implantation is performed in the well ion implantation step, it is not necessary to separately pass the well drive-in.

Claims (5)

(1) sequentially stacking an oxide film, a polycrystalline silicon layer, and a nitride film on an upper surface of a silicon substrate; (2) The oxide layer, the polycrystalline silicon layer, and the nitride layer are selectively etched, and a field oxide layer is formed on the etched portion. The oxide layer, the polycrystalline silicon layer, and the nitride layer that are not etched are removed, ; (3) a step in which the first well ion implantation, the field ion implantation, and the channel gate ion implantation are performed on the field oxide film and the gate oxide film at different energy levels; (4) applying a photoresist layer to a portion of the upper portion of the field oxide film and the gate oxide film, and performing secondary well ion implantation, field ion implantation, and channel gauge ion implantation at different energies, respectively - method for manufacturing a semiconductor integrated circuit. The method of claim 1, wherein the primary ion implantation of the well, field, and channel gates in step (3) is performed at an energy of 500 keV to 700 keV, 100 keV, 150 keV, 30 keV to 50 keV, A method of manufacturing a semiconductor integrated circuit. 2. The method of claim 1, wherein the secondary ion implantation of the well, field, and channel gate in step (4) is performed at an energy of 500 to 700 keV, 100 keV, 150 keV, 30 keV, Of the semiconductor integrated circuit. 2. The method of claim 1, wherein the P-well, N-field, and N-channel gates are formed by the first ion implantation of the well, field, and channel gates of step (3) A method of manufacturing a semiconductor integrated circuit. The method of claim 1, wherein the N-well, P-field, and P-channel gates are formed by secondary ion implantation of the well, field, and channel gates in step (4) A method of manufacturing a semiconductor integrated circuit. ※ Note: It is disclosed by the contents of the first application.