KR980012064A - A monocrystalline silicon etching method - Google Patents

Abstract

The present invention relates to a method for etching shallow trenches in single crystal silicon. The treatment etchant includes HBr / Cl ₂ / O ₂ / He. The method can be used in conjunction with various mask 24 configurations, including, for example, photoresists, oxide hard masks, and nitride hard masks. The process forms a shallow trench 32 having a width of about 0.25 microns to about 1 micron and a depth of about 0.3 microns to about 1 micron. The shallow trench 32 has a round bottom corner 38, a flat, continuous sidewall 34 and a substantially planar and clean bottom 36. For a given trench width, the profile angle is substantially uniform over the single- Do. The trench depth is substantially uniform across the single crystal silicon. Additionally, the profile angle is substantially independent of the trench length. The method may include one or both etching steps for single crystal silicon etching. The two-step etching method forms a shallow trench having a profile angle that varies with respect to the trench depth.

Description

Single crystal silicon etching method

The present invention relates to a silicon etch process, and more particularly to a dry etch process for forming shallow trenches in single crystal silicon for use in advanced integrated circuits.

Device isolation technology is important for advanced integrated circuit manufacturing. The device phase is now less than 0.5 micron and continues to be reduced to less than 0.35 micron. Current device phases already outperform many of the known isolation technologies.

One known isolation technique is the local oxidation of silicon (LOCOS) technology. The LOCOS technique includes the steps of (i) depositing a layer of Si _x N _y on a silicon substrate, (ii) selectively forming an opening through the Si _x N _y layer by reactive ion etching, and (iii) Lt; _{RTI ID =} 0.0 > SiO2 < / RTI > Pad oxides are typically provided below the Si _x N _y layer.

However, LOCOS technology has been found to be completely unsatisfactory for preparing sub-0.5 micron devices for use in high-density integrated circuits. This is because the insulation distance between the gates of the adjacent transistors must be reduced to compensate for the inherent occurrence of " buzz peak erosion " in order to grow the field oxide at a deep depth in the silicon openings. And the field oxide grows down and lifts the Si _x N _y edge The shape of the field oxide at the nitride edge resembles a birdfly The buzz peak is an extension of the field oxide in the active region of the device Buzz peak erosion It delegates the minimum isolation requirement and allows the encroachment of active devices in LOCOS technology.This problem just enforces the minimum structure size that can be achieved in LOCOS technology up to about 0.5 micron.Therefore, Device phase can not be achieved and will still be required soon in future emerging progressive integrated circuits Can not achieve device phase.

Thus, the device phase that occurs in the current and the mill of advanced integrated circuits requires other device isolation technologies to replace LOCOS technology. One other technique is trench etch mill recharging. Recharge technology is used in many VLSI (large scale integrated circuits) and ULSI (very large scale integrated circuit) applications. Trench etch and refill processes are important for the fabrication of electronic devices that develop three-dimensional structural concepts, such as trench isolation.

In such trench etch and refill techniques, the trench formation process is generally characterized as being deep, moderate or shallow trenches. Deep trenches typically have a depth of at least about 3 microns and a width of less than about 2 microns; Suitable trenches typically have a depth of from about 1 micron to about 3 microns; Shallow trenches typically have a depth of less than about one micron.

Trench etchant recharge isolation techniques that provide high performance are known as shallow trench and shallow trench and refill isolation (STI) techniques. The STI technique typically includes the steps of (i) selectively etching the overlying mask material to form a patterned mask opening for the substrate, (ii) through-etching an oxide layer overlying the silicon substrate, and (iii) (Iv) n or p-type doping the trench, (v) removing the mask material from the substrate, (vi) refilling the trench with a dielectric material, and ) Performing planarization to improve the wafer phase.

Planarization typically involves chemical-mechanical polishing and etching back to remove the mask and dielectric material on the original substrate surface to form a planar surface for fabricating the device.

The active device region is the area protected from the etchant by the mask material during formation of the trench.

The mask material is typically a photoresist or a hard mask, such as a hard mask nitride and a hard mask oxide. The photoresist mask and the hard mask are typically removed from the substrate by an acid removal process. During the chemical-mechanical polishing step, the hard mask acts as an end-point mask to prevent undesirable damage to the substrate.

It is important in STI technology to control the trench profile, the sidewall continuity and smoothness of the bottom of the trench, the smoothness and shape of the bottom corner of the trench, and minimize the etch rate and profile microloading effects. These factors are controlled by the choice of mask material provided on the silicon substrate and the processing parameters used to form shallow trenches in the substrate.

The trench profile angle typically varies from about 75 [deg.] To about 90 [deg.] In STI processing. In general, it becomes more difficult to fill the trench with a dielectric material without forming voids when the trench profile angle increases toward 90 degrees.

Considering the shape of the bottom corner of the trench, round trenches are extremely advantageous in minimizing stresses associated with defects and electrical leakage.

The trenches are also advantageous for device applications to have smooth, continuous sidewalls and a flat, clean trench bottom surface to maintain oxide integrity and improve device isolation performance.

Profile microloading results when the cross-sectional profile of a shape changes as a function of the spacing between shapes on the substrate. It is preferable that the etching process forms a shape having a uniform cross section irrespective of the distance between the density of the shape or the shape.

In the trench etch process, it is highly desirable to achieve maximum uniformity of the trench depth and trench profile angle across the wafer as well. Especially. It is preferred that both the trench depth and the trench profile angle be constant between the center and the edge of the wafer. A uniform trench depth can uniformize device performance across the wafer. Additionally, the trench profile is preferably independent of the trench depth, and as a result, the trench depth does not limit the trench profile angle that can be achieved in the trench etch process.

The known trench etch process precisely controls the trench profile angle and the shape of the trench bottom corner in the single crystal silicon shallow etch process and forms a smooth, continuous trench sidewall, a flat and clean trench bottom surface, minimizes the etch rate and profile microloading effect Can not be achieved.

Thus, a substantially uniform trench profile angle across silicon for (i) a round trench bottom corner, (ii) a substantially uniform trench depth across the silicon, (iii) a predetermined trench width, (iv) There is a need for a method for forming shallow trenches in monocrystalline silicon that provides a trench profile, (v) smooth and continuous trench sidewalls, and (vi) a flat and clean trench bottom.

It is an object of the present invention to provide a method for etching shallow trenches in monocrystalline silicon satisfying the need.

Figure 1 shows a sequential step of a typical shallow trench isolation process.

FIG. 2 shows a shallow trench profile formed by a two-step main etch process according to the present invention. FIG.

3 shows a single crystal silicon furnace having an unopened mask prior to etching; Fig.

FIG. 4 is a vertical cross-sectional view of an apparatus suitable for carrying out the process of the present invention. FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

22: single crystal silicon organ 32: trench

34a, 34b:

In particular, the method includes the steps of: (i) a substantially uniform trench profile angle across the silicon for a round trench bottom corner, (ii) a substantially uniform trench depth across the silicon, (iii) a predetermined trench width, (iv) (V) a smooth, continuous trench sidewall, and (vi) a flat, clean trench bottom.

Additionally, the method proceeds substantially without a profile of the yaw angle, undercutting, notching or trenching.

The method of the present invention includes shallow trench etching in monocrystalline silicon. The method comprises:

(a) introducing a process gas composed of a chlorine-containing compound, at least one compound selected from the group consisting of a fluorine-containing compound and a boron-containing compound, and oxygen into an etching zone;

(b) generating a plasma from the process gas; And

(c) contacting the single crystal silicon with the plasma to form a shallow trench.

The shallow trench typically has a depth from about 0.3 microns to about 1 micron and a trench width from about 0.25 microns to about 0.35 microns and typically has an angle from about 75 degrees to about 90 degrees. The shallow trench is characterized as having a smooth, continuous sidewall, a constant depth across the monocrystalline silicon, a profile angle independent of the trench depth, and a rounded bottom corner.

In the process gas, a chlorine-containing compound is typically a C _l2. These compounds are the major etchants for etching silicon. The boron-containing compound is typically HBr. When added together with _{Cl 2} , these compounds are secondary gases that primarily deactivate the trench sidewall for profile angle control.

The process gas preferably includes O ₂ promoting the formation of a rounded lower corner in the shallow trench that provides inertness and oxidation effects. The oxygen is typically introduced into the etch zone along with an inert diluent gas, such as He.

To form a shallow trench, the monocrystalline silicon has a mask thereon. The mask may be patterned or not open. The method can be used, for example, to etch single crystal silicon having various mask configurations, including a photoresist mask and an oxide and nitride hard mask. An anti-reflective coating may be provided on the mask.

The cathode temperature in the etch chamber is typically maintained at about 10 캜 to about 85 캜 and preferably at about 60 캜. The increased cathode temperature forms a shallow trench with a more vertical trench profile, reduced profile microloading, increased single crystal silicon etch, and increased bottom corner rounding.

The pressure used in the treatment is typically from about 20 mTorr to about 150 mTorr, more preferably about 60 mTorr.

The inert gas and O ₂ flow into the chamber at a total flow rate of about 5% to about 30% of the total process gas flow rate. High flow rates generally promote the formation of rounded lower corners. Helium is added as a diluent for O ₂ at a ratio of He: O ₂ of about 7.3.

The RF power level used is typically from about 200 watts to about 750 watts, preferably from about 300 watts to about 400 watts, for 6 inch to 8 inch wafer processing. Lower power levels reduce profile microloading, reduce the profile taper of wider trenches, and increase lower corner rounding.

The method may comprise two main etching steps for etching monocrystalline silicon. The first step forms an upper sidewall portion having a substantially vertical taper. The second step forms the lower sidewall portion having a larger taper than the upper sidewall portion. The second step is to use a process gas containing oxygen to use the lower corner with rounded shallow trenches.

1A-1D, a flow diagram of a sequential step of a typical shallow trench isolation (STI) method is shown.

The method is typically performed on a patterned wafer 20 comprising a substrate 22 and a superimposing mask 24.

The substrate 22 is made of monocrystalline silicon. The polycrystalline silicon is typically a wafer for use in advanced integrated circuit devices. The substrate 22 has a top surface 30.

The illustrated mask 24 includes a two-layer structure. The layer 926 on the upper surface 30 of the substrate 22 includes a layer of nitride material such as Si3N4 having a lower SiO2 and a pad oxide layer (not shown). The layer 28 disposed on the layer 26 may be comprised of a photoresist material.

The mask 24 provided on the monocrystalline substrate 22 may be changed. The preferred preferred mask 24 configuration comprises a first layer (typically a pad oxide) of the mask 24 formed directly on the top surface 30 of the substrate 22, and a second layer The remaining layers being formed: pad oxide / nitride / oxide; Pad oxide / nitride / photoresist; And a pad oxide / nitride on the monocrystalline silicon substrate 22.

The nitride layer typically has a thickness of about 1000 ANGSTROM to 3000 ANGSTROM, more preferably about 1500 ANGSTROM. The nitride layer is characterized as having a high hardness. Such layers are typically deposited using chemical vapor deposition (CVD) techniques.

The pad oxide layer is typically formed between the substrate 22 and the nitride layer to compensate for the high hardness of the nitride layer. The pad oxide layer typically has a thickness of from about 150 ANGSTROM to about 250 ANGSTROM.

The mask 24 further includes an organic antireflective coating to reduce refractory notched standing wave and backscattering light during the photolithographic process, maximize the photoresist exposure range, and optimize the photoresist sidewall profile. A preferred mask 24 comprising an antireflective coating comprises the following layer: pad oxide / nitride / antireflective coating / photoresist.

Preferred organic anti-reflective coatings are commercially available under the trademark " ARC " from Brewer Sccience, The photoresist is substantially resistive to etching so that portions of the substrate 22 covered by the photoresist pattern are not etched during the etching of the substrate 22.

Referring to FIG. 1B, the method according to the present invention includes etching of a shallow trench, such as the shallow trench 32 shown in the substrate 22. The shallow trench 32 includes opposing sidewalls 34, trench bottom 36, and trench bottom corner 38. The shallow trench typically has a minimum width of about 0.25 microns to 1 micron and has a depth of about 0.3 microns to about 1 micron. For shallow trenches having a width of about 0.25 microns to about 0.35 microns, the shallow trench sidewalls typically have a profile angle [alpha] of about 75 [deg.] To about 90 [deg.] With respect to the single crystal silicon surface 30. [

In accordance with the present invention, the shallow trench etch process typically includes an initial breakthrough etch step and a one- or two-step single crystal silicon etch referred to herein as " main etch ".

The break etching step is performed to remove any native oxide from the surface 30 of the monocrystalline substrate 22. Preferred dry etchant for the break through etch step is CF _4. Other suitable etchants may be used.

In the one-step main etching process for the single crystal silicon substrate 22, the shallow trenches 32 are formed by two separate etching steps. Referring to FIG. 2, the first etching step forms a vertical upper sidewall portion 34a in the silicon substrate 22 substantially. Next, the second etching step forms the lower side wall portion 34b to be tapered and the lower corner 38 which is rounded. The interface 34c may be formed at a position of change between the steel side wall portion 34a and the lower side wall portion 34b. This interface can be smoothed, for example, by ramping the process pressure.

According to the present invention, a two-step main etch is preferred for several reasons of the one-step main etch. First, one-step etching simplifies the main etch process by removing the etch step. Consequently, the processing time can be reduced. Second, the first stage process eliminates the interface formation between the upper and lower sidewall portions.

In both the first stage and second stage shallow trench etch processes, the formed trench preferably has a rounded lower corner 38, as shown in FIGS. 1B and 3, respectively. The rounded lower corner provides a point of minimizing stresses associated with defects and electrical leakage. As also shown in Figure IB, the shallow etch process may be performed to provide smooth and continuous contact between the sidewalls 34,34a, 34c and the flat, clean trench bottom surface < RTI ID = 0.0 > (36).

Referring to FIG. 1C, the photoresist layer 28 is removed from the layer 26 using a conventional removal solution such as H ₂ SO ₄ / H ₂ O ₂ prior to recharging the shallow trenches with the dielectric material 40. Can be removed. Following removal of the photoresist, the wafer 20 is immersed in a diluted HF solution typically to remove any of the rejuvenating material present on the sidewall 34.

The dielectric material is typically an SiO _2. Other dielectric materials may optionally be used to refill the shallow trenches 32. The dielectric material 40 is typically deposited in the shallow trench 32 using CVD techniques. As shown, the deposited dielectric layer 40 fills the trench 32 and extends on the layer 26.

1D, planarization is typically performed by depositing the dielectric material 40 on the layer 26 to form the top surface 42 of the dielectric material 40 with the top surface 27 of the layer 26 Is performed. This leveling is achieved by a general chemical-mechanical polishing step. During this step, the layer 26 may function as an endpoint mist.

With planarization, the nitride and pad oxide are removed sequentially for device processing.

Referring to FIG. 4, a reaction apparatus 50 suitable for carrying out the present invention includes an etching chamber 52 having an etching zone 54. The process gas is introduced into the etching chamber 52 through the gas inlet 58. The process gas then passes through a " showerhead " diffuser plate 60 that dispenses the process gas into the etch zone 54. The surrounding focus ring 62 substantially retains the plasma generated within the etch zone 54.

The vertical wall or pumping plate 48 defines a plurality of exhaust holes 72a and 72b and separates the etching chamber 52 into two zones: the etching zone 54 and the non-etching zone 74. The exhaust holes 72a and 72b are in fluid through the exhaust port 76 and through a vacuum pump (not shown) to exhaust the spent process gas and volatile etch byproducts from the etch chamber 52.

The reaction chamber 50 can be magnetically enhanced. A magnetic coil 80 may be provided around the etch chamber 52 to magnetically enhance the plasma formed from the process gas in the etch zone 54.

During operation, a substrate 10 as shown in FIG. 1A is disposed on the cathode 56 and process gas is introduced into the etch chamber 52 through the gas inlet 58. Plasma is generated from the process gas in the zone 54 to etch the substrate 22. The flow of the plasma is represented by arrows 82a and 82b.

According to the present invention, the process gas used in the main etch process for single crystal silicon etching comprises at least one of a boron-containing gas, a chlorine-containing gas, and a fluorine-containing gas.

The chlorine-containing gas is typically a C _l2. These gases are the main etchants for etching monocrystalline silicon.

The boron-containing gas is typically HBr. When _C12 is added, this gas is a secondary gas that primarily deactivates the trench sidewall for the phobe angle control.

The fluorine-containing gas may be, for example, SF ₆ , CF ₄ , or NF ₃ .

Oxygen is the preferred form of the O _2. The oxygen increases the deactivation of the sidewalls 34 of the shallow trenches 32 and also oxidizes the single crystal silicon substrate 22. This deactivation and oxidation enhances the rounding of the trench bottom corner 38.

The process gas preferably further comprises an inert diluent gas, typically He. A mixture of helium and oxygen gas gasses referred to herein as " He-O ₂ " is commercially available.

The process gas micro-masking (micromasking) fluoro coming effective amount of for the removal of-containing gas may include, for instance one or more of CF _4, SF _6, NF ₃ or the like. Micro-masking can limit the taper of the shallow trench for a given structure size that can be achieved in a shallow trench etch process using a process gas comprising HBr / Cl ₂ / He-O ₂ . For example, the addition of CF ₄ gas for this process configuration can be such that to remove the micro-loading, and a greater degree of taper achieved for shallow trench sidewalls.

For example, a taper of less than about 75 may be achieved for about 0.3 micron structure by this addition. Typically, the process gas flow _{90sccm HBr / 30sccm Cl 2 / 20sccm} He-O 2 / 10sccm fluorine-containing gas.

The amount of the fluorine-containing gas added when the excess portion of such gas can form a sidewall in the substantially shallow trench is precisely controlled. Thus, the fluorine-containing gas is preferably added to the process gas only when microloading occurs.

The process gas is altered by adjusting the overall gas flow rate of HBr / Cl ₂ / He-O ₂ , the flow ratio of HBr / Cl ₂ , and the overall flow ratio of He-O _{2 to} the overall flow of the process gas.

For 8 inch wafers, the overall flow rate of the process gas is typically between about 80 sccm and about 200 sccm.

The flow ratio of the HBR / Cl ₂ is generally from about 1: 1 to about 10: 1, typically about 3: 1. This ratio can be varied to change the shallow trench profile. The flow ratio of HBr / Cl ₂ has only a minimal effect on the trench profile for a fairly tapered shallow trench.

The volume ratio of He-O ₂ is typically about 7: 3. Such mixtures are commercially available.

The overall flow rate of the He-O ₂ is typically from about 10 sccm to about 40 sccm, preferably from about 15 sccm to about 30 sccm. The high flow rate of He-O ₂ promotes the formation of the lower trench corner. Also, the high flow rate of He-O ₂ increases the throughput by increasing the single crystal silicon etch rate. He-O ₂ total flow increase above about 15 sccm does not significantly change the shallow trench profile.

Because of the photoresist mask, the typical etch rate for the single crystal silicon is typically about 2500 A / min to about 4000 A / min.

The overall flow of He-O ₂ is preferably from about 10% to about 20% of the total flow of the process gas to achieve a clear corner rounding. When the total flow of He-O ₂ increases to about 20 sccm or more, micro-masking of etch by-products and polymer on the surface of the single crystal silicon occurs.

In the two-step main etch process, He-O ₂ is typically added to the process gas in the second main etch step and not added during the first step. The second etching step forms the lower portion of the shallow trench including the trench bottom corner, and thus He-O ₂ is added during this step to enhance the rounding of the trench bottom corner.

The plasma is generated from the process gas to etch the monocrystalline silicon substrate 22 in the etching step. The power used to generate the plasma is typically about 200 watts and about 750 watts, typically 400 watts. Low power levels generally provide the advantage of reducing the profile taper in wider trenches, reducing profile microloading, and increasing the trench bottom corner rounding in the wider trench in nature. The power reduction also reduces the etching rate of the single crystal silicon substrate.

The plasma may be enhanced using, for example, electron resonance resonance, a magnetically enhanced reactor, and an inductively coupled plasma. Preferably, a magnetically enhanced ion reactor is used. The magnetic field in the reaction device 50 induced by the magnetic coil 80 must be strong enough to increase the ion density formed in the plasma. The magnetic field on the surface of the single crystal silicon substrate 22 is generally from about 10 Gauss to about 80 Gauss, typically about 30 Gauss.

The pressure in the etching chamber 2 is typically about 20 mTorr to about 150 mTorr, preferably about 60 mTorr. The pressure significantly affects the localized trenching and convex shape of the bottom surface of the trench. This undesirable effect occurs at low pressures due to enhanced ion bombardment near the lower corner of the trench. Higher pressure effectively can provide a significantly tapered profile. A pressure of about 60 mTorr achieves a smooth trench bottom surface and tapered sidewalls. The pressure used also depends on the mask configuration.

The temperature of the cathode 56 affects the occurrence of a shallow trench profile and microchannel loading. The cathode temperature is typically maintained at about 10 [deg.] C to about 85 [deg.] C, preferably about 60 [deg.] C. The increased cathode trench profile angle reduces profile microloading, increases single crystal silicon etch rate and improves trench bottom rounding.

The method according to the present invention achieves a high degree of etch rate uniformity for various mask configurations. Preferably, the process achieves an etch rate non-uniformity of less than about 3% of the monocrystalline silicon for photoresist masks, gyro hardmask masks, and oxide etch masks.

The method according to the invention also achieves a high degree of etch depth uniformity in single crystal silicon. In particular, the method achieves less than about 3% etch depth non-uniformity across a single crystal silicon substrate for a shallow trench width of less than about 0.25 microns to less than 1 micron.

Additionally, other methods in accordance with the present invention achieve a high degree of shallow trench profile angular uniformity in single crystal silicon. For a given trench width, the method achieves a uniform profile angle across the single crystal silicon substrate for a shallow shallow width substantially in the range of 0.25 microns to 1 micron.

Example

The following examples demonstrate the efficiency of the invention for forming shallow trenches in single crystal silicon.

This example is performed using a 6 " or 8 inch MxP polysilicon etch chamber on a " Precision 5000 " platform of a magnetically enhanced reactive ion reactor, specifically Applied Materials,

The tested wafers are 6 inches (150 mm) (Examples 1-22) and 8 inch (200 mm) (Examples 23-37) monocrystalline silicon wafers having a (100) orientation. Several wafer mask configurations are evaluated to determine their effect on process results.

Following the etching process, the wafer is evaluated. Specifically, the sidewall profile is determined using a trench depth trench width including angled bottom flatness and bottom corner rounding, and a Hitachi motel S-4500 scanning electron microscope (SEM) of trench profile. Additionally, the selectivity of the etchant (Si: mask) was evaluated using an SEM photolithography, photolithography and a Prometmic UV-1050 thin film thickness measurement system.

Examples 1-12

In Examples 1-12, a hard mask oxide is formed on monocrystalline silicon. The mask used in this embodiment includes a continuous 110 Å pad oxide / 2000 Å SiN / 1500 Å oxide on a monocrystalline silicon substrate. The mask is patterned. The treatment conditions used are given in Table 1 below.

In Examples 1-3, a one-step main etch process (" ME ") is performed on the masked wafer. The process gas comprises HBr / C _l2 and does not contain He-O _2. Embodiment 1 is selected as the initial processing configuration. Trenching and bowing occur.

In Example 2, the pressure is reduced to 20 mTorr and the etching time is reduced to 70 seconds. The trench exhibits a vertical profile of only about 3700A and a shallow depth.

The etch time is increased in Example 3 to correct for such a shallow trench depth. The trench has a vertical profile, a sharp, non-rounded bottom corner, and an increased depth of about 4000A.

In Examples 4 and 5, a two-step main main etch process is performed on the wafer using HBr / Cl ₂ process gas. &Quot; ME1 " represents the first major etching step and " ME2 " represents the second major etching step.

Example 4 is performed in an attempt to increase the degree of rounding of the bottom corner of the trench. An increase in the HBr / Cl ₂ ratio in the second main etching step does not result in a significant improvement in the bottom corner rounding. A profile angle of about 89.5 DEG and a trench depth of about 4000 ANGSTROM are obtained.

The addition of Example 5 from the second main etch step HBr / Cl ₂ ratio reduction has no measurable effect on the lower corner rounding. A slightly curved profile is obtained.

In Example 6, He-O ₂ is added to the process gas only in the second main etching step. The He-O ₂ addition improves the rounding of the bottom corner of the trench compared to Example 1-5 where He-O ₂ is not added to the process gas. A trench profile angle of about 88 DEG -89 DEG and a trench depth of about 4350 ANGSTROM are measured.

Example 7 involves HBr / Cl ₂ / He-O ₂ treatment only in only one major etching step using TM. The resulting trench does not have a vertical top sidewall portion. Another micro loading occurs.

In Embodiment 8, the time of the second main etching step is increased, and the ratio of the time of the first step to the time of the second step is reduced. The obtained shallow trench has an upper sidewall angle of 87 degrees or more and an improved lower corner rounding as compared to Example 6.

Example 9 is reduced to a flow ratio of 3: 1 to 1: 1 HBr / Cl ₂ in the second main etching step. There is no effect that can be measured on the obtained bottom corner corner roundness. Additionally, a slight curved profile is generated.

Example 10 is increased to a total flow rate of 10 sccm to 20 sccm in the second main etching step. The increased flow rate of the He-O ₂ improves the trench bottom corner rounding.

Example 11 is performed to determine the effect of reducing power from 400 watts to 200 watts in the second main etching step. There is no measurable improvement in the obtained shallow trench profile.

Example 12 demonstrates the effect of increasing the magnetic field from 30 gauss to 100 gauss in the second main etching step. A taper is obtained at the lower portion of the increased side wall.

Examples 13-17

Examples 13-17 are performed to evaluate the effect of the photoresist mask on the shallow trench formed in the etching process. The mask used in this case includes the following continuous layer: 110 Å pad oxide / 2000 Å Si _x N _y / 3100 Å photoresist. The mask is patterned. The processing conditions used in this example are given in Table 2 below.

In Examples 13-16, the etching process is included in a single main etching step, and the process gas contains HBr / Cl ₂ and does not contain He-O ₂ . Embodiment 13 is an initial processing configuration. Considerably tapered trench sidewalls with angles less than 80 [deg.] Are observed.

In Example 14, the pressure is increased from 20 mTorr to 80 mTorr. A slightly tapered profile of about 87 degrees and a trench payoff of about 4150 angstroms are formed.

In Example 15, the wall is further increased to 90 mTorr. An enhanced vertical profile of 87 DEG or more is formed.

In Example 16, the pressure is further increased to 100 mTorr. A slight eccentricity of about 2650A and a very shallow trench are obtained.

Example 17 is included in the two-step main etching. He-O ₂ is added to the process gas in the second etching step. The resulting trench has a depth of 4600 angstroms, an improved profile with a vertical top sidewall having an angle of greater than about 87 degrees, a bottom sidewall tapered to about 77 degrees, and a rounded lower corner.

Examples 18-22

Examples 18-22 evaluate the effect of a hard mask nitride on a shallow trench formed in an etch process. The mask used in this embodiment is included in the following continuous layer: 110 Å pad oxide / 2000 Å hard nitride.

The mask is patterned. The processing conditions used in this example are given in Table 3 below.

In Examples 18-20, the etching process is included in a single main etching step and the process gas contains HBr / Cl ₂ and does not contain He-O ₂ . Example 18 is an initial processing setting. A significantly tapered trench sidewall is formed.

In Example 19, the etching time is reduced and the pressure is reduced to 100 mTorr. The resulting trenches are shallow, have a depth of about 3800 angstroms, and have a slightly < RTI ID = 0.0 >

In Example 20, the etching time is increased over that of Example 18, and the pressure is reduced to 50 mTorr. The trench has a depth of about 5850 angstroms at a profile angle of 86 degrees.

In Examples 21 and 22, the two-step main etching step is used to increase the rounding of the bottom corner of the trench. The shallow trench formed in Example 21 above shows an improved profile with a vertical top sidewall and a rounded bottom corner. In Example 22, the pressure reduction to 20 mTorr in the second etching step results in the formation of an upper sidewall portion having a profile angle of greater than about 87 degrees, and the smoothness of the lower corner is improved.

Examples 1-22 demonstrate the effect of mask construction on the results of the etching treatment according to the present invention. For ideal HBr / Cl ₂ / He-O ₂ processing conditions, the trench sidewall profile angle and trench bottom corner rounding (e.g., taper reduction) increase in the order of photoresist / hard mask nitride / hard mask oxide. The pressure is further increased to 100 mTorr. In addition, the etch rate for the photoresist is lower than for the hard mask nitride and the hard mask oxide.

Examples 23-33

In Examples 23-33, a single crystal silicon wafer having an open mask was evaluated. The mask comprises a 150 Å pad oxide / 2000 Å hard mask nitride / 800 Å antireflective coating / 5000 Å photoresist formed continuously on a monocrystalline silicon substrate. The processing conditions used are shown in Table 4 below.

This embodiment is performed to test the effects of He-O ₂ flow, pressure, RF power and cathode temperature on the resulting shallow trench profile and microloading effect.

The breakthrough etching step is used in Examples 23-28 and 30-33 to remove the residual pad oxide resulting from the provisional mask opening process and the predetermined noble oxides on the single crystal silicon substrate. The etchant used in this step is CF ₄ .

Example 23 is performed on a scale up to an 8 inch wafer size process based on two stage 6 inch process conditions. The process gas includes HBr / Cl ₂ / He-O ₂ / NF ₃ in the main etching step.

Example 24 includes a two-step main etch to obtain a vertical top sidewall and a round trench bottom corner. The first stage main etching process is performed in Examples 26 and 27 where Hr-O ₂ is not added to the process gas and in Examples 25-28 and 30-33 in which He-O ₂ is added to the process gas.

The results from Examples 23-33 change the effect on the resulting shallow trench profile and etch rate microloading.

The results for Example 33 are given in Tables 5 and 6.

As shown in Table 5, the one-step main etch process of Example 33 achieves a predetermined trench width over the monocrystalline silicon substrate at an upper, even profile angle, in particular a nominal trench width in the range of 0.25 microns to 0.30 microns.

As shown in Table 6, the processing parameters of Example 33 also achieve a high degree of trench depth uniformity for nominal trench widths ranging from about 0.25 microns to about 1.0 microns. The trench depth non-uniformity is less than about 3.1% for this range of trench widths. Additionally, the shallow trenches exhibit smooth, continuous sidewalls, a rounded lower corner, a flat bottom and no warpage.

The etch rate of about 2670 ANGSTROM / min for the single crystal substrate was measured in Example 33.

Referring to the He-O ₂ flow, the results for Examples 23-33 demonstrate that high He-O ₂ flow rates achieve rounded bottom corners of the trench. In Example 33, an etch rate of 2670 A / min achieves a He-O ₂ flow of 15 sccm.

The pressure is proven to have the effect of removing the concave trench bottom surface and the sharp bottom corner in the wider trench. Higher pressure removes the formation of concave lower trenches. However, excess pressure is disadvantageous for the trench sidewall taper. In Example 28, the pressure of 60 mTorr of the main etch step is greater than the angle of about 80 degrees for the planar trench sidewall lower surface, and for the process 0.25 micron trench and about 65 degrees for the 1 micron trench for all trench sizes The branches achieve significantly tapered sidewalls.

The above embodiments demonstrate that a high cathode temperature improves sidewall taper and reduces profile microloading. To minimize the profile micron loading between the nominal 0.25 micron and 1 micron shape of Example 28, the cathode temperature is increased to 60 占 폚 in Examples 31-33. The resulting trench profile angle is improved to about 85 degrees for a nominal 0.25 micron trench and to about 73 degrees for a 1 micron trench.

Considering the RF power used in the etch process, low power is determined to minimize profile microloading. In Examples 32 and 33, the RF power is reduced from 600 watts to 400 watts in Example 31. The reduced RF power is more effectively reduced in the profile taper over a wider trench than a narrow trench. The low power also increases the lower corner rounding in Example 33. Resulting in a reduced single crystal silicon etch rate of 2670 A / min. As shown in Table 5, a prison pile angle of 86 ° is achieved at a nominal 0.25 micron trench and a profile angle of 77 ° is achieved at a nominal 1 micron trench.

Some of the notches are observed at the top of the trench profile in Examples 23-33. This is caused by a large amount of polymer deposition on the mask prior to the main trench etch and during the main trench etch.

A large amount of sidewall deposition is formed by a mask opening process. It is believed that the sidewall deposition is more in the wider open area. Consequently, the deposited polymer is eroded during the main trench etch and the larger notched corners are driven in wider trenches.

Additionally, some debris caused by microloading is observed. It is believed that such debris is caused by an incomplete nitride mask opening process.

Examples 34 and 35

A combined in-situ mask opening and shallow trench etch process is evaluated for the two wafers. 3, the masks in Examples 34 and 35 include a pad oxide 90 / nitride hard mask 92 / antireflective coating 94 / photoresist 96 on the single crystal silicon substrate 22 ). ≪ / RTI > These layers have a thickness of 150 Å pad oxide / 2000 Å nitride hard mask / 800 Å antireflective coating / 7500 Å photoresist. The patterned photoresist layer defines an opening (x) of about 0.25 microns to about 1 micron in size. The processing conditions used are given in Table 4.

The antireflective coating (" BARC ") is etched using a CF ₄ / He-O ₂ etchant. The nitride is etched using a SF ₆ etchant in the main etch step and the overetch step. In a main etch step for a single crystal silicon substrate to form shallow trenches, the etchant comprises HBr / Cl ₂ / He-O ₂ .

The etch rates and selectivity results for the antireflective coatings and nitride etch steps of Examples 34 and 35 are shown in Table 7.

Example 35 forms a smooth trencher sidewall, a bottom of a planar trench, and a rounded corner. Additionally, no residue and no upper notching are observed. A somewhat rounded shallow trench upper corner results.

Based on Example 35, the process according to the present invention is an effective in-situ mask opening and a shallow trench etch process for single crystal silicon wafers.

Therefore, the present method for etching shallow trenches in monocrystalline silicon requires substantially uniform (uniform) trench width over silicon for (i) rounded trench bottom corner, (ii) substantially uniform trench depth across silicon, and (Iv) a trench profile independent of the trench depth, (v) a smooth, continuous trench sidewall, and (vi) a flat, clean trench bottom.

In addition, the present invention does not form a profile of the yaw angle, undercutting, notching or trenching.

Furthermore, the present invention can be used to etch single crystal silicon having different mask configurations.

The present invention can include one or two major etching steps depending on the desired shallow trench profile.

The present invention also provides effective in-situ mask opening and shallow trench etch processing for single crystal silicon wafers.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be apparent to those skilled in the art.

Claims (33)

A method of single crystal silicon etching comprising: (a) introducing a process gas comprised of HBr, Cl _2, and oxygen into an etch zone; (b) generating a plasma from the process gas; And (c) contacting the plasma with the monocrystalline silicon. The method of claim 1 wherein the single crystal silicon etching method which is characterized in that the process gas comprises O _2. 3. The method of claim 2, wherein the process gas further comprises an inert gas. 4. The method of claim 3, wherein the inert gas is helium. 2. The method of claim 1, wherein the process gas further comprises a fluorine-containing gas. A shallow trench etch process in monocrystalline silicon, comprising: (a) disposing a monocrystalline silicon having a patterned mask in a chamber; (b) introducing a process gas comprising a chlorine-containing compound, at least one compound selected from the group consisting of a fluorine-containing compound and a boron-containing compound, and oxygen into an etching zone; (c) generating a plasma of the process gas in the chamber; And (d) etching the shallow trench into the single crystal silicon by contacting the single crystal silicon with the plasma in the chamber. 7. The shallow trench etch process as claimed in claim 6, wherein the boron-containing compound is HBr. Claim 6, wherein the chlorine-containing compound can be a shallow trench etching in the single-crystal silicon, characterized in that Cl _2. The method of claim 6, wherein the fluorine-bearing compound is CF _4, SF _4, and shallow trench etching in the single-crystal silicon, characterized in that it comprises a compound selected from the group consisting of NF _3. 7. The method of claim 6 wherein the process gas is HBr, Cl _2, and the shallow trench etching in the silicon single crystal, comprising a step of including oxygen. 7. The method of claim 6, wherein the mask is selected from the group consisting of a photoresist mask, an oxide hard mask, and a nitride hard mask. 7. The method of claim 6 wherein the process gas is a shallow trench etching in the silicon single crystal comprising the O _2. 7. The method of claim 6 wherein the process gas is a shallow trench etching in the single-crystal silicon, characterized in that it comprises an inert gas and O _2. 14. The shallow trench etch process as claimed in claim 13, wherein the inert gas is He. The method of claim 13 wherein the process gas is the fluoride of HBr, Cl ₂ and the effective amount to remove the micro-masking-etching a shallow trench in a single crystal silicon, comprising containing compounds. 7. The method of claim 6, wherein the shallow trench has a depth of about 0.3 microns to about 1 micron. 17. The method of claim 16, wherein the shallow trench has a width of about 0.25 microns to about 0.35 microns and a sidewall profile angle of about 75 degrees to about 90 degrees. 7. The method of claim 6, wherein the shallow trench has a round bottom corner and a flat bottom. 7. The method of claim 6, wherein the shallow trench has smooth, continuous sidewalls. 7. The method of claim 6, wherein the shallow trench has a constant depth across the single crystal silicon. 7. The method of claim 6, wherein the shallow trench has a sidewall profile angle that is independent of the depth of the shallow trench. 7. The method of claim 6, wherein the disposing step comprises disposing the monocrystalline silicon on a cathode having a temperature of about 10 < 0 > C to about 85 < 0 > C. 7. The method of claim 6, wherein the pressure in the chamber is from about 20 mTorr to about 150 mTorr. 14. The method of claim 13, wherein an inert gas and O ₂ is the entire flow rate to the total flow rate of about 5% to about 30% of the shallow trench etching in the single-crystal silicon, characterized in that introduced into the chamber of the process gas. 11. The method of claim 10, wherein HBr vs. flow rate of Cl ₂ is about 1: 1 to about 10: shallow trench etching in the single-crystal silicon, characterized in that one. 7. The method of claim 6, wherein the plasma generating step comprises applying an RF current having a power level between about 200 watts and about 750 watts. 7. The method of claim 6, wherein the contacting comprises anisotropically etching the single crystal silicon to form a shallow trench. A shallow trench etch process in monocrystalline silicon, comprising: (a) disposing a monocrystalline silicon having a patterned mask in a chamber; (b) the step of introducing a first processing gas consisting of HBr and Cl ₂ in the chamber; (c) generating a first plasma of the first process gas in the chamber; And (d) contacting the monocrystalline silicon with the first plasma in the chamber to etch an upper trench portion having an upper sidewall portion at a first profile angle to the monocrystalline silicon; (e) generating a second plasma of a second process gas comprised of HBe, Cl _2, and oxygen; (f) entering the second plasma of the second process gas in the chamber; And (g) contacting the single crystal silicon with the second plasma in the chamber to etch a lower trench portion having a lower sidewall of a second profile angle in the single crystal silicon, wherein the upper sidewall portion and the lower sidewall portion Wherein the trench comprises a sidewall of the trench, wherein the trench comprises a bottom and a bottom corner of the trench. 29. The method of claim 28, trench etching in the single-crystal silicon, characterized in that the second process gas comprises O _2. The method of claim 28, wherein the second process gas in the single crystal silicon trench etching process comprising the inert gas and O _2. 29. The method of claim 28, wherein the first profile angle is greater than or equal to the second profile angle. 32. The method of claim 31, wherein the lower corner of the trench is rounded. A shallow trench etch process in monocrystalline silicon comprising: (a) disposing monocrystalline silicon in a chamber; (b) introducing into the chamber a process gas comprising HBr, Cl ₂ and an inert gas and O ₂ ; (c) generating a plasma of the process gas in the chamber; And (d) contacting the single crystal silicon with the plasma in the chamber to etch shallow trenches in the monocrystalline silicon, wherein the shallow trenches comprise trench-opposed sidewalls, a bottom wall and a bottom corner, (I) a rounded lower corner, (ii) a uniform trench length and trench profile angle across the single crystal silicon for a given trench width, (iii) a trench sidewall angle independent of the trench depth, (iv) , And (v) a flat bottom. ※ Note: It is disclosed by the contents of the first application.