KR980011451A - Semiconductor memory device capable of mode designation in an active state - Google Patents

Abstract

The present invention relates to a semiconductor memory device capable of mode designation in an active state, and more particularly to a semiconductor memory device capable of designating a mode in response to a mode switching control signal, First latch means for latching a mode command signal that has passed through the first switch means; Second switching means for switching a mode command signal latched in said first latch means in response to a delay control signal; And second latch means for latching a mode command signal through the second switch means and outputting a mode designation signal.

Therefore, in the present invention, the MRS is set in the active state to prevent the malfunction, and the control signal for inputting the column address at the time of setting the MRS signal is given as Do not care so as to simultaneously perform the precharging and the MRS, There is an effect that can be specified.

Description

Semiconductor memory device capable of mode designation in an active state

The present invention relates to a semiconductor memory device capable of designating a mode in an active state and more particularly to a semiconductor memory device capable of preventing a malfunction that may occur in selecting an operation mode by a mode changeover control signal when a bank is in an active state, To a semiconductor memory device capable of mode designation in an active state.

Since the mode switching device can selectively enable a specific operation mode among preset operation modes of the semiconductor memory and can select a specific operation mode after combining signals inputted from the outside, Devices.

1 is a circuit diagram showing the configuration of a mode switching control circuit of a semiconductor memory device according to the related art. The switch circuit 20 (see FIG. 1) for transferring a mode command signal in response to a mode switching control signal And a latch means 40 which is a storage device for storing a mode command signal transmitted by the switch unit 20. [

FIG. 2 shows a mode switching control signal generating means and a free-charge control signal generating means according to the prior art, and includes a chip select burst (CSB), a row address strobe buster A Column Address Strobe Burst (CASB), and a Write Enable Burst (WEB) are input as control signals of a NOR gate. The MRS signal is active when CSB, RASB, CASB, and WEB are both low level. Since CSB, RASB, and WEB are all at the low level and the CASB is at the high level, the precharging is performed. The arming means loads the inverter to the CASB input terminal and executes the precharge instruction.

In the conventional circuit as described above, it is prescribed that all the banks in the memory should be free-charged when the MRS is input. Therefore, when the MRS is set, the switch unit 20 is turned on and the mode command signal Ai is supplied to the latch unit (40) and designates the mode. However, in the case of an operation in which the operation mode needs to be changed frequently, the free timing instruction must be given before the MRS is performed, so that the timing becomes long.

Therefore, when all the banks are set in the active state other than the free-charge state, the timing becomes longer, and an undesired malfunction occurs.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device capable of preventing erroneous operation caused when a bank is switched from an active state to a mode transition state and delivering command timing at a high speed, Device.

According to an aspect of the present invention, there is provided an apparatus including a first switch unit for transmitting a mode command signal in response to a mode switching control signal, MRS, a first latch unit for temporarily latching a mode command signal transmitted through the first switch unit, A second switch for transmitting a mode command signal stored in the first latch in response to a delay control signal and a second switch for storing data of a mode command signal transmitted through the second switch, And a second latch.

FIG. 1 is a circuit diagram showing a configuration of a mode switching control circuit of a semiconductor memory device according to a related art; FIG.

Fig. 2 is a diagram showing a mode switching control signal generating means and a precharging control signal generating means of the prior art;

FIG. 3 is a circuit diagram showing a configuration of a mode switching control circuit of a semiconductor memory device according to the present invention; FIG.

FIG. 4 is a view showing the mode switching control signal generating means and the free charge control signal generating means of the present invention; FIG.

FIG. 5 is a waveform diagram for explaining the operation of the mode switching control circuit according to the present invention; FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

100: first switch unit 120: first latch

140: second switch unit 160: second latch

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention.

FIG. 3 is a circuit diagram of an embodiment of a semiconductor memory device capable of specifying a mode in an active state according to the present invention. The semiconductor memory device includes an input terminal for receiving a mode command signal, a first switch unit 100 responsive to MRS, A first switch 120 for temporarily storing a mode command signal transmitted to the switch unit 100 and a second switch unit 140 for transmitting the data value stored in the first latch 120 in response to a DMRS signal, And a second latch 160 for storing data transferred through the second switch unit 140 and outputting an output value designating a mode.

In response to the high level of the MRS signal, the transfer gate M1 of the first switch unit 100 is turned on to transfer a signal input from the outside, and a dynamic control signal The second switch unit 140 is turned on by the mode register set (DMRS) to temporarily store the mode command signal in the first latch 120, and the second switch unit 140 to the second latch 160 and outputs an output value designating a mode. When both the MRS and the DMRS are down to the low level, the transfer gate Ml of the first switch unit 100 responding to the MRS and the second switch unit 140 responding to the DMRS are turned off, Lt; / RTI >

When the MRS rises to the high level and the DMRS changes to the low level state, the first switch unit 100 driven in response to the MRS is turned on and the second switch unit 140 driven in response to the DMRS Transmission gate M2 is turned off and stores a mode command signal in response to the newly set MRS signal in first latch 120.

FIG. 4 is an MRS and a free-guard input logic gate according to the present invention. FIG. 4 is an active state when CSB, RASB, CASB, and WEB are all low level and CSB, RASB, In the present invention, the precharge is performed by setting the control signal for inputting the column address CASB to Do not care.

As a result, when the MRS signal is set, the present invention simultaneously performs the free-charge function, and when another row (Row) is active, it switches to a new operation mode. If the mode command is a valid data I / O value, the MRS is delayed until the data transfer is completed.

That is, the command for setting the free charge instruction and the MRS signal to all the banks of the memory device is reduced to one MRS signal, and the timing for setting the MRS signal after the precharge instruction is shortened, so that the operation mode is switched to high speed.

FIG. 5 is a waveform diagram for explaining the operation of the mode switching control circuit according to the present invention. When a bank of a memory which can be independently read or written to the main memory device is active, At this time, the DMRS remains at the high level state. When the MRS signal for performing the write command in synchronization with the up edge of the input clock signal is set, the DMRS executes the data write command at the down edge and the data input at the up edge of the DMRS, And stores the data in the second latch 160.

The MRS signal for executing the lead instruction is set in synchronization with the up edge of the clock signal and the DMRS is executed in the state of the down edge so that the data stored in the first latch 120 and the second latch 160 is read And the free-charge MRS signal is synchronized with the up-edge of the clock signal, and the data output is performed at the up-edge of the DMRS.

However, when a new MRS signal is set and input during data write and read instructions, a new MRS signal is stored in the first latch 120, so that data write and read commands are continuously performed and the first latch 120 Is stored in the second latch 160 and is switched to the new operation mode. Thereafter, the write or read command of the data is performed in the new operation mode.

The lines a, b, and d shown in the figure show that the MRS signal is set in synchronization with the input clock signal. The c and e lines are changed only after the mode switching device finishes the data lead- Lt; RTI ID = 0.0 > 120 < / RTI >

In the prior art, when an MRS is performed in an active state, an operation mode such as a burst type and a burst length in which data transfer is continuously performed in synchronization with an input clock signal specified by a mode switching device is performed in a data lead- If the MRS signal is set in the active state, the command timing required to set the MRS signal can be reduced. In addition, since the operation mode frequently changed by using the MRS is required to be free-charge + MRS + active The operation mode can be switched while maintaining the active state, thereby reducing the timing at which the operation mode is switched.

The present invention prevents erroneous operation that occurs when an operation mode is designated in an active state, sets timing for performing free guard and MRS commands by simultaneously performing free guard and MRS by setting CASB to Do not care at the time of setting an MRS signal So that the operation mode can be designated at a high speed.

Claims (3)

First switching means for switching a mode command signal in response to a mode switching control signal; First latch means for latching a mode command signal that has passed through the first switch means; Second switching means for switching a mode command signal latched in said first latch means in response to a delay control signal; And second latch means for latching a mode command signal through the second switch means and outputting a mode designation signal. 2. The semiconductor memory device according to claim 1, wherein the delay control signal is a signal for blocking a signal latched by the first latch means from being transmitted to the second latch means during a lead and a write operation, A possible semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the apparatus comprises: first switch means for generating a mode switching control signal in which a chip select signal, a row address strobe signal, a column address strobe signal, and a write enable signal are all active; And a second switch means for generating a free charge control signal in an active state of a chip select signal, a row address strobe signal, and a write enable signal. ※ Note: It is disclosed by the contents of the first application.