KR980011439A - A semiconductor memory device having a plurality of reference voltage generators - Google Patents

Abstract

The present invention relates to a semiconductor memory device having a plurality of reference voltage generators. The present invention is a semiconductor memory device having a memory cell array region and a peripheral circuit region including auxiliary means necessary for driving the memory cell array, wherein the internal power supply voltage used in the memory cell array region, Each of the reference voltage generators having a voltage level of an internal power supply voltage used in an area and a voltage level of the internal power supply voltage being different from each other, The ratio of the resistor divider is the same, the voltage levels of the input reference voltages are different from each other, and the voltage levels of the output signals of the reference voltage generators are different from each other. Therefore, the semiconductor memory device having a plurality of reference voltage generators according to the present invention can minimize changes to external changes including process variations, and thus can reduce the variation of the output signals of the respective reference voltage generators There is an advantage that voltage level can be obtained.

Description

A semiconductor memory device having a plurality of reference voltage generators

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a plurality of reference voltage generators.

Much effort has been made to keep the power consumed by the chip constant while the memory device is highly integrated and the area of the chip is increased. At the same speed, 16M DRAM (DRAM) and 256M DRAM must also have the same power consumption, and so far we have tried to solve this problem by lowering the power supply voltage level. In other words, two power sources are created inside the chip, one is used for the peripheral circuits related to the speed, and the other is used for the memory array, and the power supply voltage level is adjusted as needed.

The two internal power supplies are designed to receive an external power supply (External VCC) supplied from the outside and have a constant voltage in a certain region of the external power supply. At this time, the voltage levels of the two types of internal power supplies may be different. However, the schemes for generating the two internal power sources are the same.

The two internal power supplies (hereinafter referred to as VREFAs and VREFPs) generate VREFAs and VREFPs, respectively, at a constant ratio using a reference voltage of VREF. When the voltage levels of VREFA and VREFP are not different from each other, the ratio of VREFA to VREFP is similar to that of VREF. However, when the difference between the voltage levels of VREFA and VREFP is large, the ratio of VREFA to VREFP . It is difficult to design the ratio of VREFA and VREFP to VREFF against VREF in order to generate VREFAs and VREFPs using only one VREF in view of the same scheme for generating VREFAs and VREFPs and receiving the same process change do. Because the rate of change of VREFA and VREFP is different for a process change, it is difficult to match both the voltage levels of VREFA and VREFP to the target specification at the same time.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor memory device having a plurality of reference voltage generators capable of solving the problems of the prior art.

1 is a general structural view of a semiconductor memory device;

FIG. 2 is a circuit diagram of a reference voltage generator for an array and a reference voltage generator for a peripheral circuit according to an embodiment of the present invention; FIG.

According to an aspect of the present invention, there is provided a semiconductor memory device having a plurality of reference voltage generators, including: a semiconductor memory device having a memory cell array region and a peripheral circuit region including auxiliary means necessary for driving the memory cell array; Wherein each of the reference voltage generators determines a voltage level of the internal power supply voltage that is different from an internal power supply voltage used in the memory cell array region and an internal power supply voltage used in the peripheral circuit region, And each of the reference voltage generators has the same ratio of the resistor divider that determines the voltage level of the output signal, and the voltage levels of the input reference voltages are different from each other.

The voltage levels of the output signals of the reference voltage generators are different from each other.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a general structure of a semiconductor memory device, which includes a cell array 1 portion in which a plurality of blocks composed of a plurality of memory cells are arranged, a word line selecting means and bit line selecting means of the cell array 1, And a peripheral circuit 3 for controlling the operation of the internal signal.

The semiconductor memory device generally uses the array voltage VREFA for controlling the internal power supply of the cell array 1 and the peripheral circuit voltage VREFP for controlling the peripheral circuit 3 separately. In general, the array voltage (VREFA) has a close relationship with the consumed current. Therefore, it is required to have a voltage as low as possible and the peripheral circuit voltage (VREFP) is closely related to the operating speed. Which is a known fact.

FIG. 2 is a circuit diagram of a reference voltage generator for an array and a reference voltage generator for a peripheral circuit according to an embodiment of the present invention.

Referring to FIG. 2, the internal power supply voltage used in the memory cell array region of the memory device of FIG. 1 and the voltage level of the internal power supply voltage used in the peripheral circuit region are different from each other, The reference voltage generator 10 for the array, and the reference voltage generator 20 for the peripheral circuit.

The reference voltage generators 10 and 20 for the arrays and peripheral circuits have the same ratio of resistors and transistors Q1 and Q2 for determining the voltage levels of the output signals VREFA and VREFP, The reference voltage VREF_VREFA,

VREF_VREFP are configured to have different voltage levels, and the voltage levels of the respective output signals VREFA and VREFP are different from each other.

The reference voltage generators 10 and 20 for the array and the peripheral circuits are provided with a differential amplifier stage 1 for comparing the reference voltages VREF_VREFA and VREF_VREFP with voltage levels of the node A and differential amplifier stages 10a and 20a Transfer sections 10b and 20b for supplying electric charges to the respective output signals VREFA and VREFP according to the result of comparison between the voltage of the node A and the voltage of the node A due to the distribution of the turn- And a resistance distribution portion 10c, 20c for making a level. The voltage levels of the output signals VREFA and VREFP generated here are respectively VREF_VREFA * (resistance ratio of Q1 and Q2) and VREF_VREFP * (resistance ratio of Q1 and Q2).

When the reference voltage generators 10 and 20 for powering up the array and peripheral circuits are powered up and a predetermined time has elapsed, the voltage level of the node A is lowered to the respective reference voltages V1 and V2 at the differential amplifier stages 10a and 20a If the voltage level of the node A is higher than the reference voltages VREF_VREFA and VREF_VREFP, the transistor Q3 is turned off so that the voltage levels of the output signals VREFA and VREFP are lowered And when it is lower than the reference voltages VREF_VREFA and VREF_VREFP, the transistor Q3 is turned on so that the voltage responsiveness of the output signals VREFA and VREFP increases. The voltage levels of the output signals VREFA and VREFP are kept constant while repeating such operations.

Here, there is no problem if the voltage levels of VREFA and VREFP, which are the output signals of the array reference voltage generator 10 and the peripheral circuit reference voltage generator 20, are the same. However, as mentioned above, When the voltage level of VREFP is different and only one reference voltage that is the same as the reference voltage of the array reference voltage generator 10 and the peripheral circuit reference voltage generator 20 is used, The ratio Q1 / Q2 of the transistor Q1 to the transistor Q2 in the circuit reference voltage generator 20 is different from each other. This means that the change ratio of Q1 / Q2 is different for VREFA and VREFP with respect to the external change including the process change, so that the voltage level of VREFA and VREFP can not be generated according to the target design specification.

Therefore, in order to solve such a problem in the present invention, as shown in FIG. 2, the ratio of Q1 / Q2 of the resistor distribution sections 10c and 20c of the array reference voltage generator 10 and the peripheral circuit reference voltage generator 20 is By using the same reference voltages (VREF_VREFA, VREF_VREFP) with different voltage levels, it is possible to minimize the variation of the ratio of Q1 / Q2 to external variations including process variations, The voltage levels of VREFA and VREFP can be obtained.

For example, if the target voltage levels of VREFA and VREFP are 2.2V and 2.4V, respectively, if the ratio of Q1 / Q2 is 2, the level of the reference voltage VREF_VREFA of the array reference voltage generator 10 is 1.1V , And the level of the reference voltage VREF_VREFP of the peripheral circuit reference voltage generator 20 is 1.2V. In this case, since the ratio of Q1 / Q2 in each of the reference voltage generators 10 and 20 is constant, the ratio of Q1 / Q2 does not change even if there is a process change, so that the voltage levels of VREFA and VREFP are constant.

Therefore, the semiconductor memory device having a plurality of reference voltage generators according to the present invention can minimize a change in the ratio of Q1 / Q2 to an external change including a process change, And the voltage level of VREFP can be obtained.

It is apparent that the present invention is not limited to the above-described embodiments, and that various modifications can be made by those skilled in the art within the technical scope of the present invention.

Claims (2)

1. A semiconductor memory device having a memory cell array region and a peripheral circuit region including auxiliary means necessary for driving the memory cell array, wherein the internal power supply voltage used in the memory cell array region and the peripheral circuit region used in the peripheral circuit region Each of the reference voltage generators having a voltage level of the internal power supply voltage different from the voltage level of the internal power supply voltage and determining the voltage level of the different internal power supply voltages, And the plurality of reference voltage generators are different from each other in voltage levels of input reference voltages. The semiconductor memory device according to claim 1, wherein the voltage levels of output signals of the reference voltage generators are different from each other. ※ Note: It is disclosed by the contents of the first application.