KR980007004A - Application Integrated Circuit (ASIC) and Implementation Method for High-speed Interprocessor Communication - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an application integrated circuit (ASIC) serving as a frame address filter in a large-capacity inter-processor communication board (HINA) used for switching between high-speed processors in CDMA mobile communication switching centers, In order to accommodate the maximum number of subscribers, to enable multiple data transmission, and to duplicate control of the system, an exchange of the mobile communication system, an application circuit for communication between the base station and the control station in the HINA board, (ASIC) and an implementation method thereof; It is possible to accommodate the maximum number of subscribers of the CDMA system and eliminate bottlenecks caused by data congestion. In addition, when a system failure occurs, the system can be doubly controlled to improve reliability, So that the overall system configuration is simplified.

Description

Application Integrated Circuit (ASIC) and Implementation Method for High-speed Interprocessor Communication

Since this is a trivial issue, I did not include the contents of the text.

FIG. 2 is a block diagram of an application specific integrated circuit (ASIC) according to the present invention; FIG.

FIG. 3 is a detailed view of the main part of FIG. 2 of the present invention. FIG.

FIG. 4 is a flowchart of a first step of two-point communication frame path control of the present invention. FIG.

5 is a flowchart of a third step of two-point communication frame path control according to the present invention;

FIG. 6 is a second stage flowchart of the multicasting communication frame path control of the present invention.

Claims (11)

An application specific integrated circuit (ASIC) serving as a frame address filter in a large inter-processor communication board (HINA) used for high-speed processor-to-processor communication, wherein the application integrated circuit (ASIC) An address management unit (21) for providing an output signal to be used for path control by using the address signal; A frame address control unit 22 for transferring data to the processor by using addresses and attributes provided by the address management unit 21 and addresses provided within the node; A processor matching unit 23 for generating various signals managed by an external processor for node control and signals for operation in an integrated circuit (ASIC); A fault management unit (24) for transmitting a FAULT interrupt generated by an external node buffer controller (NBC); And a bus occupancy arbitration unit (25) for controlling bus occupancy between nodes. The application integrated circuit (ASIC) for high speed interprocessor communication. 2. The apparatus of claim 1, wherein the frame address control unit (22) comprises: input frame data registers (22-1, 22-1 ') for receiving frame data and detecting a start flag; A forced insert '0' bit elimination unit 22-2 for searching for and removing the '0' bit among the destination addresses transmitted from the frame data registers 22-1 and 22-1 '; A data mapping processing unit 22-3 for receiving a pure address through the '0' bit removing unit 22-2 and reconstructing a position of a frame address to be used for path control; Message frame path control units (22-4 # 1- # 8) for controlling the path according to the reconfigured address and control signal and transmitting the operation signal (BRXEN-B) to the corresponding node buffer controller (NBC); And a frame transmission control unit (22-5) for delaying a data clock by a path control time through a common data bus and a data clock signal and transmitting the delayed data clock to an external node buffer controller (NBC). Application Integrated Circuit (ASIC). A high level data link control (HDLC) frame used to enable interprocessor communication in a mobile communication network, wherein a maximum number of subscribers is accommodated using a 3-byte address scheme. (ASIC). In system control during high-speed processor-to-processor communication in a mobile communication system, hardware control for generating a fault in the event of a failure of each signal of the communication board, and software control for switching the duplicated bus, A method for implementing an application specific integrated circuit (ASIC) for high speed interprocessor communication. A method of implementing an application integrated circuit (ASIC) for communication between high-speed processors, characterized in that a path control for a communication frame between two points and a path control for multicasting are operated in controlling a path of a communication frame . 6. The method of claim 5, wherein the path control of the two-point communication frame comprises: a first step (S1) of bit-by-bit path control using an attribute for path control; A second step (S2) of checking the overall result value of the general mode and the test mode comparison result; And a third step S3 for controlling the communication path by using the result of the second step S2 and the bit arbitration and node test related control signals. Implementation method. 7. The method of claim 6, wherein the first step (S1) of the path control operation of the two-point communication frame is to check the corresponding mask attribute (MA) bit of the received message frame address and set (T1) for setting a test mode comparison result (PCOB) for a corresponding bit and a mode comparison result (PCOA), and a control attribute bit (PCOB) for a corresponding bit if the mask attribute is reset in the first step CO) and, if reset, a second step (T2) of comparing the received frame address bits with the address bits AD of the node itself; If the comparison result in the second step (T2) is the same value, both the normal mode comparison result and the test mode comparison result are set, and if the result is different, the second- A first step (T2-1); A third step (T3) of comparing the received frame address and the address AD of the node itself among the set bits when the control attribute bit (CO) is set in the second step (T2); And a third step (T3-1) of setting a normal mode comparison result when the comparison result is the same in the third step (T3) and setting the general mode comparison result when the comparison result is different in the third step (T3) A method for implementing an application specific integrated circuit (ASIC) for high speed interprocessor communication. 7. The method of claim 6, wherein the third step (S3) of the path control operation of the two-point communication frame comprises: a first step (U1) of inspecting an input signal (DUP) indicating a characteristic of the node itself; A second step (U2-1) of checking a test mode path control state signal (TEST-B) when the processor is a node connected in the first step (U1); A third step (U3-1) of checking the path control type (ASEL-B) when the test mode path control state is set in the second-first step (U2-1); If the path control type (ASEL-B) is checked by the path control of the normal mode comparison in the 3-1 step (U3-1), the state of the normal mode path control result (PCONA) is checked. A fourth step (U4-1) of allowing reception of a frame if it is in a reset state; If the path control type (ASEL-B) is determined by the path control of the test mode comparison in the 3-1 step (U3-1), the test mode path control result (PCONB) is checked. A 4-2 step (U4-2) of not accepting frame reception if it is reset; If the test mode path control state has been reset in the second stage (U2-1), the normal mode path control result (PCONA) of the second stage (S2) is checked. If it is confirmed as the test result set, (Step U4-3) of allowing reception of a frame if the frame is confirmed as a reset, The test mode control unit 200 checks the test mode path control status signal TEST-B if the characteristic of the node itself is a bridge node in the first step U1, A second step (U2-2) of transitioning to a path control state and determining whether to receive a frame according to the result; The bus occupation state signal BASTOUT-B is monitored when the status signal TEST-B is reset in the second-2 < th > step U2-2, and the third -2 step (V3-2); When the bus occupation state signal BASTOUT-B is reset in the step 3-2 (V3-2), the normal mode path control result (PCONA) is checked. If the bus state signal BASTOUT-B is set, (U4-4) in which the reception of the frame is prohibited. The method of claim 1, further comprising: 6. The method of claim 5, wherein the routing of the multicasting communication frame includes a first step of detecting a flag for multicasting (S1 '), a step of inputting a result from the first step (S1' And a second step (S2 ') for controlling a path of a data frame. 2. The method as claimed in claim 1, The method as claimed in claim 9, wherein the first step (S1 ') of detecting a multicasting flag in the path control operation of the multicasting communication frame includes setting the first address address byte of the received frame, ), The second address byte is set and the broadcasting frame flag FMAD2 is set, the upper 4 bits of the second byte of the frame address and the 4 bits of the multicasting control attribute in the node are compared for each bit The network flag NFLAG for multicasting is set if there is a corresponding bit of the same value even after one bit, and the multicast network flag NFLAG is reset when all corresponding four bits are different, An application specific integrated circuit (ASIC) / RTI > The method as claimed in claim 9, wherein the second step S2 'of the multicast communication frame path control operation checks the state of the multicasting communication frame flag FMAD1 and the multicasting control signal BMCON-B, A first step (V1) of inspecting a characteristic (DUP-B) of the node itself; A second step (V2-1) of checking a node test node path control state (TEST-B) when the node is a processor node of the node in the first step (V1); If the bus occupation state signal BASTOUT-B is checked in step 2-1 (V2-1), the bus occupation state signal BASTOUT-B is checked. If the bus occupation state signal BASTOUT-B is not in the corresponding state, (V3-1); In step 3-1, the broadcast control signal FMAD2 is checked in the third step (V3-1). If it is set, the multicast network flag CA [3: 0] is checked. If it is set, (4-1) (V4-1) in which frame reception is prohibited if the frame is allowed and reset; If the path control state between the test modes is reset in the second-first step (V2-1), the state of the bus occupancy state signal (BASTOUT-B) is checked. If the check result is set, -2 step (V3-2); (4-2) (V4-2) for checking the state of the broadcasting communication flag (FMAD2) if the checking result is reset in the step (3-2) (V3-2) ; A fifth step (V5-1) of checking the state of the network flag (NFLAG) in the reset state in the step 4-2 (V4-2) and disallowing the frame reception if the state is reset; If the result of status check of the network flag NFLAG in step 5-1 is V5-1, the lower 4 bits (F [11] to F [8]) of the second byte on the frame address and the multicasting control The lower four bits CA [3] to CA [0] of the attribute bytes are compared on a corresponding bit basis. If they are all the same, the frame reception is permitted. If there is at least one different bit, Step (V6-1); If the node itself is a bridge node in the first step (V1), the test mode path control state (TEST-B) is checked and if it is set to the second mode (V2- 1) (V2-2); If it is determined in the step 2-2 (V2-2) that the test result is the reset state, the frame transmission status signal (BASTOUT-B) for the data bus is checked. If the check result is set, Step (V3-3); If the frame transmission status signal BASTOUT-B for the data bus is reset in the 3-3 step (V3-3), the status of the network flag NFLAG is checked. If the status is reset, Step 4-3 (V4-3); In the case of the set state in the step 4-3 (V4-3), the lower four bits CA [3] to CA [0] of the multicasting control attribute bytes of the node itself are checked and all are set to '0' (V5-2) in which reception of a frame is permitted and reception of a frame is prohibited if any bit is set to " 1 ". The integrated circuit (ASIC).