KR980006832A - Low-pass 11R filter design method and low-pass 11R filter - Google Patents

Low-pass 11R filter design method and low-pass 11R filter Download PDF

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Publication number
KR980006832A
KR980006832A KR1019960025217A KR19960025217A KR980006832A KR 980006832 A KR980006832 A KR 980006832A KR 1019960025217 A KR1019960025217 A KR 1019960025217A KR 19960025217 A KR19960025217 A KR 19960025217A KR 980006832 A KR980006832 A KR 980006832A
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South Korea
Prior art keywords
output
adder
delay unit
shifter
delay
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KR1019960025217A
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Korean (ko)
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KR100195220B1 (en
Inventor
이제석
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김광호
삼성전자 주식회사
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Priority to KR1019960025217A priority Critical patent/KR100195220B1/en
Publication of KR980006832A publication Critical patent/KR980006832A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0223—Computation saving measures; Accelerating measures
    • H03H17/0225—Measures concerning the multipliers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0223—Computation saving measures; Accelerating measures
    • H03H17/0227—Measures concerning the coefficients
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0223—Computation saving measures; Accelerating measures
    • H03H17/0238—Measures concerning the arithmetic used
    • H03H17/0241—Distributed arithmetic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H2017/0072—Theoretical filter design
    • H03H2017/009—Theoretical filter design of IIR filters

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  • Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Picture Signal Circuits (AREA)
  • Filters That Use Time-Delay Elements (AREA)

Abstract

본 발명은 저역통과 ⅡR 필터의 설계방법 및 이에 적합한 저역통과 ⅡR필터를 개시한다. 본 발명의 장치는 입력신호 x(n)를 입력받아 소정시간 지연시키는 지연기(21)와, 지연기(21)의 출력을 MSB측으로 1비트 시프트하는 시프터(22)와, 지연기(21)의 출력을 소정시간 지연시키는 지연기(23)와, 출력신호 y(n)을 입력받아 소정시간 지연시키는 지연기(24)와, 지연기(24)의 출력을 MSB측으로 2비트 시프트하는 시프터(25)와, 지연기(24)의 출력을 소정시간 지연시키는 지연기(26)와, 지연기(23)의 출력에서 시프터 (25)의 출력을 감산하는 감산기(100)와, 감산기(100)의 출력에서 시프터(22)의 출력을 감산하는 감산기(200)와, 입력신호 x(n)와 감산기(200)의 출력을 가산하는 가산기(300)와, 가산기(300)의 출력과 계수 c를 승산하는 승산기(350)와, 지연기(24)의 출력에서 지연기 (26)의 출력을 감산하는 감산기(400)와, 감산기(400)의 출력과 계수 2t를 승산하는 승산기(450)와, 승산기(350)의 출력과 승산기(450)의 출력을 가산하는 가산기(500)와, 가산기(500)의 출력과 지연기(26)의 출력을 가산하는 가산기(600)로 구성된다.The present invention discloses a method of designing a low-pass IIR filter and a low-pass IIR filter suitable for the method. The apparatus includes a delay unit 21 for receiving an input signal x (n) and delaying the input signal x (n) for a predetermined time, a shifter 22 for shifting the output of the delay unit 21 by 1 bit toward the MSB, A delay unit 24 for delaying the output of the delay unit 24 by a predetermined time, a delay unit 24 for delaying the output signal y (n) by a predetermined time, and a shifter A subtracter 100 for subtracting the output of the shifter 25 from the output of the delay unit 23; A subtracter 200 for subtracting the output of the shifter 22 from the output of the adder 300 and an adder 300 for adding the output of the subtracter 200 to the input signal x A subtractor 400 for subtracting the output of the delay unit 26 from the output of the delay unit 24, a multiplier 450 for multiplying the output of the subtractor 400 by a coefficient 2t, multiplication An adder 500 for adding the output of the multiplier 350 to the output of the multiplier 450 and an adder 600 for adding the output of the adder 500 and the output of the delay 26. [

여기서,Wp는 임계주파수, T는 샘플링시간이다. 따라서, 본 발명은 승산기의 갯수가 감소함으로 인하여 하드웨어의 크기가 작아지는 이점이 있다.here, W p is the critical frequency, and T is the sampling time. Therefore, the present invention has an advantage that the size of the hardware is reduced because the number of multipliers is reduced.

Description

저역통과11R필터의 설계방법 및 이에 적합한 저역통과11R필터Low-pass 11R filter design method and low-pass 11R filter

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 본 발명에 의한 저역통과 ⅡR필터의 구성을 보인 도면.FIG. 2 is a view showing a configuration of a low-pass IIR filter according to the present invention; FIG.

Claims (2)

임게주파수(Wp)와 샘플링주기(T)를 입력받아 아날로그 주파수(WA)를 계산하는 제1단계; 아날로그 주파수(WA)를 입력받아 아날로그 영역에서의 시스템 전달함수(H(S))를 바이리니어 변환법에 의하여 디지탈 영역에서의 시스템 전달함수(H(Z))로 변환하는 제2단계; 디지탈 영역에서의 시스템 전달함수(H(Z))로 부터 차분방정식(y(n))을 구하는 제3단계; 차분방정식(y(n))의 계수(a,b,c)를 최적화하여 새로운 차분방정식(y'(n)을 구하는 제4단계; 및 차분방정식 (y'(n)을 만족하는 버터워스 필터를 구현하는 제5단계를 포함함을 특징으로 하는 저역통과 ⅡR필터의 설계방법. A first step of receiving an input frequency W p and a sampling period T and calculating an analog frequency W A ; A second step of receiving the analog frequency W A and converting the system transfer function H (S) in the analog domain into the system transfer function H (Z) in the digital domain by the bilinear transformation; A third step of obtaining a differential equation y (n) from the system transfer function H (Z) in the digital domain; A fourth step of obtaining a new differential equation y '(n) by optimizing coefficients a, b and c of the differential equation y (n) and a fourth step of calculating a new differential equation y' And a fifth step of implementing the low pass IIR filter. 여기서,here, 입력신호 x(n)를 소정시간 지연시키는 제1지연기와, 상기 제1지연기의 출력을 MSB 측으로 1비트 시프트하는 제1시크터와, 상기 제1지연기의 출력을 소정시간 지연시키는 제2지연기와, 출력신호 y(n)을 입력받아 소정시간 지연시키는 제3지연기와, 상기 제3지연기의 출력을 MSB 측으로 2비트 시프트하는 제2시프터와, 상기 제3지연기의 출력을 소정시간 지연시키는 제4지연기와, 상기 제2지연기의 출력과 상기 제2시프터의 출력을 가산하는 제1가산기와, 상기 제1가산기의 출력에서 상기 제1시프터의 출력을 가산하는 제1가산기와, 입력신호 x(n)와 상기 제1가산기의 출력을 가산하는 제2가산기와, 상기 제2가산기의 출력과 계수 c를 승산하는 제1승산기와, 상기 제3지연기의 출력과 상기 제4지연기의 출력을 감산하는 제3감산기와, 상기 제3감산기의 출력과 계수 2t를 승산하는 제2승산기와, 상기 제1승산기의 출력에서 상기 제2승산기의 출력을 감산하는 제2감산기와, 상기 제2감산기의 출력과 상기 제4지연기의 출력을 가산하는 제4가산기를 포함함을 특징으로 하는 저역통과 ⅡR필터.A first delay unit for delaying the input signal x (n) by a predetermined time; a first selector for shifting the output of the first delay unit by one bit toward the MSB; and a second delay unit for delaying the output of the first delay unit by a predetermined time A third delay for receiving the output signal y (n) and delaying it for a predetermined time; a second shifter for shifting the output of the third delay by 2 bits toward the MSB; A first adder for adding an output of the first shifter to an output of the first adder; a second adder for adding an output of the second shifter to an output of the second shifter; A first multiplier for multiplying an output of the second adder by a coefficient c; a multiplier for multiplying the output of the third delay and the output of the fourth delay < RTI ID = 0.0 > A third subtractor for subtracting the output of the third subtracter from the output of the third subtractor and a coefficient 2t A second subtracter for subtracting the output of the second multiplier at the output of the first multiplier and a fourth adder for adding the output of the second subtractor and the output of the fourth delayer / RTI > low-pass IIR filter. 여기서, here, , WP는 임계주파수, T는 샘플링시간 , W P is the critical frequency, T is the sampling time ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960025217A 1996-06-28 1996-06-28 Design method of low pass iir filter and low pass iir filter KR100195220B1 (en)

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KR1019960025217A KR100195220B1 (en) 1996-06-28 1996-06-28 Design method of low pass iir filter and low pass iir filter

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KR1019960025217A KR100195220B1 (en) 1996-06-28 1996-06-28 Design method of low pass iir filter and low pass iir filter

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KR100195220B1 KR100195220B1 (en) 1999-06-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101121217B1 (en) * 2011-10-14 2012-03-22 주식회사 스마트송 Apparatus for estimating pitch in time domain using iir filter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101121217B1 (en) * 2011-10-14 2012-03-22 주식회사 스마트송 Apparatus for estimating pitch in time domain using iir filter

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