KR0151147B1 - Digital high pass filter - Google Patents

Abstract

None.

Description

Digital high pass filter

1 is a block diagram of a first embodiment of the present invention.

2 is a block diagram of a second embodiment of the present invention.

3 is a block diagram of a third embodiment of the present invention.

4 is a frequency characteristic diagram used for explaining the third embodiment of the present invention.

5 is a block diagram of a fourth embodiment of the present invention.

6 is a block diagram of a fifth embodiment of the present invention.

7 is a block diagram of a sixth embodiment of the present invention.

8 is a block diagram of an example of an averaged digital low pass filter.

9 is a frequency characteristic diagram of an example of an averaged digital low pass filter.

10 is a block diagram of another example of an averaging digital low pass filter.

11 is a block diagram of an example of a conventional digital high pass filter constructed based on an averaged digital low pass filter.

12 is a frequency characteristic diagram of an example of a digital high pass filter constructed based on an averaged digital low pass filter.

* Explanation of symbols for main parts of the drawings

1, 21, 41, 61, 81, 101: input terminal

2, 22, 44, 64, 84, 104: m sample delay circuit

3, 23: (m + 1) sample delay circuit

4, 8, 24, 28, 45, 65, 85, 105, 109: Subtraction circuit

6, 7, 26, 27, 47, 50, 67, 70, 87, 90, 107, 110: addition circuit

10, 30, 52, 7, 92, 112: output terminal

The present invention relates to a digital high pass filter suitable for detecting high frequency components of a video signal, in particular in an autofocus circuit of contrast detection methods.

In the digital high pass filter, the N-stage (2m) averaging low pass filter is mainly used to realize a high-pass filter of rapid characteristics, and the hardware scale is reduced by simplifying the delay circuit and simplifying the counting circuit. .

BACKGROUND ART An autofocus circuit is known which detects a mid-range component in a video signal, integrates a dual high-band component within a predetermined focus area to obtain an evaluation value, and positions the lens to maximize the evaluation value.

In conventional autofocus circuits of this kind, analog high pass filters are used to detect mid-range components in video signals. By the way, the analog high pass filter is affected by the temperature characteristics, and the element imbalance is large. In analog high pass filters, there is a limit to miniaturization.

Therefore, the use of digital filters has been considered for detecting mid-range components in video signals in such autofocus circuits. In a digital filter, device imbalance does not occur and temperature characteristics are not affected. Therefore, the digital filter can be miniaturized and highly reliable.

In the structure of a digital filter, an FIR type and an IIR type are well known. A typical example of the FIR filter is a transverse filter whose impulse response lasts for a finite time, cascaded unit delay circuits, and a coefficient that is added to the output of each tap. An IIR type filter generally includes a circuit so that the output signal is delayed, overlapped, fed back to the input side, and displayed again at the output side.

In the autofocus circuit, it is desired that the filter used to detect the mid-range component in the video signal has a steep characteristic. By the way, it is difficult to realize a steep characteristic as a FIR type filter or an IIR type filter.

In other words, if a steep characteristic is obtained as the FIR filter, the order becomes high and the hardware scale increases.

On the other hand, in the IIR filter, steep characteristics are obtained at a lower order than the FIR filter. By the way, if a steep characteristic is acquired as an IIR type filter, the coefficient will become close to 1, and the characteristic will become unstable. Linear phase cannot be obtained with IIR filter.

Therefore, the present inventor proposes to construct a digital pass filter based on an averaged digital low pass filter.

The transfer function H (Z) of the N-stage (2m) averaging digital low pass filter is

Represented by 8 illustrates the averaging digital low pass filter by the above equation. In addition, the term of group delay correction amount Z ^m is excluded.

In FIG. 8, one sample delay circuit 152 ₁ to 152 2m of the stage of _2m is cascaded, and the input terminal 151 is derived at the stage of the cascaded stage. The output between each stage of the delay circuits 152 ₁ to 152 _2m is supplied to the addition circuit 153. The output of the addition circuit 153 is supplied to the multiplication circuit 154 (1 / (2m + 1)). The output terminal 155 is derived from the (1 / (2m + 1)) multiplication circuit 154.

9 shows the characteristics of this averaging digital low pass filter. In this example, ((2m + 1) = 33). In FIG. 9, the solid line shows the amplitude characteristic and the broken line shows the phase characteristic.

In the averaging digital filter shown in Figure 8, of a delay circuit 152 ₁ ~152 2m or _2m, the addition circuit 153 adds the output of delay circuit 152 between each stage of the _first ~152 _2m interpolator required and the hardware is very large .

So, by transforming the equation as follows,

It is contemplated to construct an averaging digital low pass filter.

10 illustrates the averaging digital low pass filter by the above equation. The term of group delay correction (z ^m ) is excluded.

In FIG. 10, the digital signal at the input terminal 161 is supplied to the (2m + 1) sample delay circuit 162 and supplied to the addition circuit 163. In FIG. The output of the (2m + 1) sample delay circuit 162 is supplied to the addition circuit 164. The output of the addition circuit 164 is supplied to the (1 / (2m + 1)) multiplication circuit 165 and returned to the addition circuit 164 via the one sample delay circuit 166. The output terminal 167 is derived from the (1 / (2m + 1)) multiplication circuit 165.

By the delay circuit 162 and the subtraction circuit 163, calculation of (1-Z- ^{(2M + 1)} ) of the transfer function molecule shown in the expression ⁽² ) is performed. The delay circuit 166 and the adder circuit 164 calculates (1-Z ^-1 ) of the denominator with respect to the transfer function of the formula (2).

As described above, the averaging digital low pass filter transformed by the averaging digital low pass filter shown in equation (1) is configured to form an averaging digital low pass filter to simplify hardware.

The digital high pass filter can be mainly composed of the above-mentioned averaging digital low pass filter. In other words, subtracting 1 from 1 results in the characteristics of the high pass filter as shown below.

③ The equation can be modified as follows.

11 shows the high pass filter formed by the equation (4). In FIG. 11, the digital signal at the input terminal 171 is supplied to the m sample delay circuit 172, the (2m + 1) sample delay circuit 173, and to the arithmetic circuit 174. In FIG. The output of the (2m + 1) sample delay circuit 173 is supplied to the subtraction circuit 174.

The output of the subtraction circuit 174 is supplied to the addition circuit 175. The output of the addition circuit 175 is supplied to the subtraction circuit 176 and returned to the addition circuit 175 via the one sample delay circuit 177.

The output of the m sample delay circuit 172 is supplied to the (2m + 1) multiplication circuit 178. The output of the (2m + 1) multiplication circuit 178 is supplied to the subtraction circuit 176. The output of the subtraction circuit 176 is supplied to the (1 / (2m = 1)) multiplication circuit 179. The output terminal 180 is derived from the (1 / (2m + 1)) multiplication circuit 179.

The characteristics of the digital high pass filter of the transfer function shown in equation (3) or (4) are as shown in FIG. In this example, ((2m + 1) = 33). In FIG. 12, the solid line shows the amplitude characteristic and the broken line shows the phase characteristic.

As can be seen from the characteristics shown in Fig. 12, when the digital high pass filter is constituted by the averaging low pass filter, a very steep one is obtained. Therefore, such a high pass filter is suitable for use in the above-described autofocus circuit for detecting mid-range components in a video signal.

This high pass filter modifies the transfer function as shown in equation (4), and the hardware can be simplified as shown in FIG. However, even in the configuration shown in FIG. 11, the coefficient multiplication circuit 178 is required, or a multistage delay circuit is required, and the reduction in hardware scale is not sufficient. If there is a multiplication circuit, it becomes difficult to speed up.

Accordingly, it is an object of the present invention to provide a digital high pass filter that can simplify the hardware scale and realize high speed.

The present invention provides a cascade connection of a delay circuit (2) of m samples and a delay circuit (3) of a (m + 1) sample, a delay circuit of an input signal and a delay circuit of m samples (m + 1) and a sample of (m + 1). An output signal at the connection point of the first subtracting circuit 4 subtracting the delayed input signal through the cascade connection of (3) and the delay circuit 2 of the m samples and the delay circuit 3 of the (m + 1) sample. A first addition circuit that adds a coefficient (2m) multiplication circuit (5) that multiplies a coefficient (2m) by an output signal of a delay circuit (2) of m samples and a delay circuit (3) of (m + 1) samples. (6), the first one sample delay circuit 9 and the second addition circuit 7 which adds the output signal by one sample delay, and adds it to the output signal of the first subtraction circuit 4; And a second subtracting circuit 8 for calculating the output signal of the first adding circuit 6 and the output signal of the second adding circuit 7 so as to obtain an output signal at the output of the second subtracting circuit 8. One digital high pass filter.

The present invention relates to the slave circuit of the (m + 1) sample delay circuit 22 and the m sample delay circuit 23, the input signal and the m sample delay circuit, and the (m + 1) sample delay circuit 22. And a third arithmetic circuit 24 for subtracting the delayed input signal through the slave connection of the delay circuit 23 of the m samples, and a second one sample delay circuit 31 for latching the output signal of the third arithmetic circuit. a coefficient (2m) multiplication circuit (25) that multiplies a coefficient (2m) by an output signal at the connection point of the (m + 1) sample delay circuit (22) and the m sample delay circuit (23), and (m + 1) Third adder circuit 26 in which the sample delay circuit 22 and the (m + 1) sample add the output signal at the connection point of the delay circuit 23 and the output signal of the coefficient (2m) multiplication circuit 25. ), The third one sample delay circuit 32 latching the output signal of the third addition circuit 26, and the output signal are delayed by one sample and returned. Fourth fountain to add with output signal A fourth subtracting the output signal of the third delay circuit 29 and the third addition circuit 27, the fourth one sample delay circuit 29, and the output signal of the third one sample delay circuit 32; And a digital high pass filter configured to obtain an output signal at the output of the fourth subtraction circuit 28.

The present invention provides a subsidiary connection of a delay circuit 42 of a sample (m-1), a fifth sample delay circuit 43 and a delay circuit 44 of m samples, and a delay circuit of a sample (m-1). The connection point of the first coefficient m multiplication circuit 46 and the fifth sample delay circuit 43 and the m sample delay circuit 44 connected to the connection point 42 and the fifth sample delay circuit 43. A second coefficient m multiplication circuit 48, an input signal, a delay circuit 42 of the (m-1) sample, a fifth sample delay circuit 43, and a m sample delay circuit 44 connected to the second coefficient m multiplication circuit 48; A fifth subtraction circuit 45 for subtracting the delayed input signal through the first output signal, the first coefficient m multiplication circuit 46 output signal, and the fifth coefficient adding the output signal of the second coefficient m multiplication circuit 48. The sixth sample delay circuit 51 and the sixth adder circuit 50 which return the circuit 47 and its output signal by one sample delay, and add it to the output signal of the fifth subtraction circuit 45. And an output signal of the fifth adding circuit 47 and a sixth A sixth subtraction circuit 49 is provided for auditing the output signal of the addition circuit 50, which is a digital high pass filter configured to obtain an output signal at the output of the sixth subtraction circuit 49.

It is possible to realize a high pass filter having a steep characteristic mainly made up of common delay circuits, spaced coefficient circuits, and an averaged digital low pass filter.

[First Embodiment]

1 shows a first embodiment of the present invention. In FIG. 1, the m sample delay circuit 2 and the (m + 1) sample delay circuit 3 are cascaded. The input digital signal at the input terminal 1 is supplied to the subtraction circuit 4 and is supplied to the subtraction circuit 4 via the m sample delay circuit 2 and the (m + 1) sample delay circuit 3.

The output at the connection point of the m sample delay circuit 2 and the (m + 1) sample delay circuit 3 is supplied to the addition circuit 6 and supplied to the multiplication circuit 5 having a coefficient of 2 m. The multiplication circuit 5 having this coefficient of 2 m is realized by the bit shift circuit. The output of the multiplication circuit 6 is supplied to the subtraction circuit 8.

The output of the subtraction circuit 4 is supplied to the addition circuit 7. The output of the addition circuit 7 is supplied to the subtraction circuit 8 and is fed back to the addition circuit 7 via the one sample delay circuit 9. An output of the arithmetic circuit 8 is generated at the output terminal 10.

In the first embodiment of the present invention, the above-described averaging digital low pass filter mainly constitutes a digital high pass filter.

When the digital high pass filter is configured in the N stage (2m) averaging digital low pass filter, the transfer coefficient is

Becomes Then, when the hardware is developed according to the above equation, it is as shown in FIG. The first embodiment simplifies the hardware of the digital high pass filter shown in FIG.

First, in FIG. 11, the (1 / (2m + 1)) multiplication circuit 179 determines the overall gain and can be omitted. The multiplication circuit 179 is omitted, and hardware can be reduced.

In the structure shown in FIG. 11, the multiplication circuit 178 of the coefficient (2m + 1) is required. Since the multiplication circuit 178 must be configured using a multiplier, the hardware scale becomes large, and the obstacle of speed-up occurs.

The multiplication of (2m + 1) can be configured by a multiplication circuit and an addition circuit with a coefficient of 2m. A multiplication circuit with a coefficient of 2 m can be realized by a bit shift circuit. Thus, when the multiplication circuit of the coefficient (2m + 1) is comprised by the bit shift circuit and the addition circuit, reduction of a hardware scale is possible and a processing speed improves.

In the first embodiment of the present invention shown in FIG. 1, the multiplication circuit 178 of the coefficient (2m + 1) in FIG. 11 is constituted by the multiplication circuit and the addition circuit 6 having a coefficient of 2m which are used in the bit shift circuit. . This reduces the hardware scale.

In FIG. 11, the (2m + 1) sampling delay circuit 173 may be replaced by a cascade connection of the m sample delay circuit and the (m + 1) sample delay circuit. When the (2m + 1) sample delay circuit 173 is replaced with the m sample delay circuit and the (m + 1) sample delay circuit, the output of the connection point of the m sample delay circuit and the (m + 1) sample delay circuit is counted (2 m). It is supplied to the multiplication circuit 178 of +1), and the one sample delay circuit 172 can be omitted.

In the first embodiment of the present invention shown in FIG. 1, in FIG. 10, the (2m + 1) sample delay circuit 173 is replaced by the m sample delay circuit 2 and the (m + 1) sample delay circuit 3, respectively. A subordinate connection is made so that the output of the connection point of the m sample delay circuit 2 and the (m + 1) sample delay circuit 3 is supplied to the bit shift circuit and the adder circuit 6 as the multiplication circuit 5 having a coefficient of 2 m. Thus, it is possible to reduce the hardware scale.

Second Embodiment

2 shows a second embodiment of the present invention. In FIG. 2, the (m + 1) sample delay circuit 22 and the (m + 1) sample delay circuit 23 are cascaded. The input digital signal at the input terminal 21 is supplied to the subtraction circuit 24, and the subtraction circuit 24 is passed through the (m + 1) sample delay circuit 22 and the (m + 1) sample delay circuit 23. Supplied to.

The output at the connection point of the m sample delay circuit 22 and the (m + 1) sample delay circuit 23 is supplied to the addition circuit 26 and supplied to the multiplication circuit 25 having a coefficient of 2 m. The multiplication circuit 25 can be realized by a bit shift circuit. The output of the multiplication circuit 25 is supplied to the addition circuit 26.

The output of the addition circuit 26 is supplied to the one sample delay circuit 32. The output of the one sample delay circuit 32 is supplied to the subtraction circuit 28.

The output of the subtraction circuit 24 is supplied to the one sample delay circuit 31. The output of the one sample delay circuit 31 is supplied to the addition circuit 27. The output of the addition circuit 27 is supplied to the one sample delay circuit 29. The output of the one sample delay circuit 29 is fed back to the addition circuit 27 and supplied to the subtraction circuit 28. An output of the subtraction circuit 28 is generated at the output terminal 30.

The second embodiment of the present invention is intended to further simplify the configuration of the first embodiment shown in FIG.

That is, a register for latching the addition output and the subtraction output is required at the rear end of the addition circuit and the subtraction circuit. Therefore, in the case of realizing the first embodiment shown in FIG. 1, one sample delay circuit is provided at the rear end of the subtraction circuit 4, and one sample delay circuit is provided at the rear end of the addition circuit 6. The 1-sample delay circuit is installed after the 7). Since one sample delay circuit is provided at the rear end of the addition circuit 7, it is necessary to provide one sample delay circuit for delay matching at the rear end of the addition circuit 6.

In the second embodiment, the output of the adder circuit 27 is supplied to the sample delay circuit 29, and the output of the one sample delay circuit 29 is returned to the adder circuit 27 to be supplied to the subtraction circuit 28. Thus, in the first embodiment, one sample delay circuit for returning the output of the adder 7 by one sample delay and one sample delay circuit for latching the adder output of the adder 7 are one sample. It is common in the delay circuit 29. In addition, the one-sample delay circuit 22 for delay matching is omitted. In this way, reduction of hardware is realized.

Third Embodiment

3 shows a third embodiment of the present invention. In FIG. 3, the (m + 1) sample delay circuit 42, one sample delay circuit 43, and the m sample delay circuit 44 are cascaded. The input digital signal at the input terminal 41 is supplied to the subtraction circuit 45, and subtracted via the sample delay circuit 42, the one sample delay circuit 43, and the m sample delay circuit 44 (m-1). Supplied to the circuit 45.

(m-1) The output of the connection point of the sample delay circuit 42 and the one sample delay circuit 43 is supplied to the multiplication circuit 46 of the coefficient m. In addition, the multiplication circuit 46 of this coefficient m may be constituted by a bit shift circuit. The output of the multiplication circuit 46 of the coefficient m is supplied to the addition circuit 47.

The output of the connection point of the one sample delay circuit 43 and the m sample delay circuit 44 is supplied to the multiplication circuit 48 of the coefficient m. The multiplication circuit 48 of this coefficient m can be configured by a bit shift circuit. The output of the multiplication circuit 48 of the coefficient m is supplied to the addition circuit 47.

The output of the subtraction circuit 45 is supplied to the addition circuit 50.

The output of the addition circuit 50 is supplied to the subtraction circuit 49 and returned to the addition circuit 50 via the delay circuit 51. The output of the subtraction circuit 49 is taken out of the output terminal 52.

In the first and second embodiments described above, in the addition circuits 6 and 26, signals multiplied by 2 m and signals not multiplied by 2 m are added, respectively. The multiplication circuits 5 and 25 that multiply by 2 m are realized by bit shift circuits. For this reason, the word length of the signal multiplied by 2 m in the multiplication circuit 25 is longer than the data bits of the input signal by bit shifting by multiplying the data bits of the input signal by 2 m. For example (m = 16), the coefficient 2m becomes 32, which shifts the data five bits, and the data length increases by five bits. Therefore, each of the addition circuits 6 and 26 must add signals having different word lengths, and the addition circuits 6 and 26 have the number of data bits of the outputs of the multiplication circuits 5 and 25. Word length in accordance with is required. For this reason, the hardware scale becomes large.

In the third embodiment, the word lengths of the two addition input data added by the addition circuit 47 are substantially the same, so that hardware simplification can be realized in the digital high pass filter shown in FIGS. 1 and 3 described above. have.

The third embodiment is constituted of one order lower order in the above-described first and second embodiments. That is, the digital high pass filter shown in FIG. 1 and FIG. 3 mentioned above is comprised based on the averaging digital low pass filter of N stage (Zm) shown by (1) formula. It is considered to configure the digital high pass filter in the averaging digital low pass filter of the 1st stage lower than the averaging digital low pass filter shown by (1).

In the equation, the transfer function H (Z) of the first-order low-order averaging digital low pass filter is

Represented as When the high pass filter is configured in the above formula, the transfer function H (Z) is

Becomes

Considering the group region component Z ^{(M- (1/2))} is excluded, Z ^{(M- (1/2))} is good even if it cannot be realized.

By the way, if the digital high pass filter is constituted by ⑥,

Must be realized. However, since the delay of 1/2 sample is not performed, this cannot be realized with this generation.

Therefore, in the present embodiment, the following approximation is performed.

In other words, at an average of two samples before and after, the sample value of the signal in between can be estimated.

Mz ^{-((2m-1) / 2)}

Mz (mz ^{-((2m-2) .2)} + mz ^{-((2m-0) .2)} ) / 2

In this, mz ^{-((2m-1) / 2)}

Mz (mz ^{-((2m-2) 2)} + mz ^{-((2m-0) / 2))} / 2

Mz (mz- ^(m-1) + mz ^-m ) / 2. … ⑦.

Therefore, the term of (2mz ^{-((2m-1) / 2))} ) can be realized as (mz- ^(m-1) + mz ^-m ).

In the third embodiment of the present invention, hardware is constructed by the formula (6). Then, the equation 2mz ^{-((2m-1) / 2)} is obtained by the equation ⁽⁷⁾ . That is, (m-1) the output of the connection point of the sample delay circuit 42 and the one sample delay circuit 43 is supplied to the multiplication circuit 46 of the coefficient m, and the one sample delay circuit 43 and the m sample delay circuit are The output of the connection point of 44 is supplied to the multiplication circuit 46 of the coefficient m, and the output of the multiplication circuit 46 and the output of the multiplication circuit 48 are added in the adder circuit 47.

In this case, the word lengths of the output of the multiplication circuit 46 which are both addition inputs of the addition circuit 47 and the output of the multiplication circuit 48 are substantially the same. Thereby, the structure of the addition circuit 47 can be simplified. That is, the word length of the addition circuit 47 is good as (the number of bits of data + 1 bit).

4 shows a characteristic diagram in this case. In this example, the value is (2m = 32). In FIG. 4, the solid line shows the amplitude characteristic and the broken line shows the phase characteristic.

As can be seen from the characteristics shown in FIG. 4, although the high frequency component is lost in the characteristics of this configuration, it is sufficient as a characteristic for detecting the midrange component of the video signal in the autofocus circuit.

Fourth Embodiment

5 shows a fourth embodiment of the present invention. In Fig. 5, the (m-1) sample delay circuit 62, one sample delay circuit 63, and the m sample delay circuit 64 are cascaded. The input digital signal at the input terminal 61 is supplied to the subtraction circuit 65 and subtracted via the (m-1) sample delay circuit 62, one sample delay circuit 63, and m sample delay circuit 64. Supplied to the circuit 65.

(m-1) The output of the connection point of the sample delay circuit 62 and the one sample delay circuit 63 is supplied to the adder circuit 67. The output of the connection point of the one sample delay circuit 63 and the m sample delay circuit 64 is supplied to the adder circuit 67. The output of the addition circuit 67 is supplied to the multiplication circuit 66 of the coefficient m. In addition, the coefficient m can be configured by the multiplication circuit 66 by the bit shift circuit. The output of the multiplication circuit 66 is supplied to the subtraction circuit 69.

The output of the subtraction circuit 65 is supplied to the addition circuit 70.

The output of the addition circuit 70 is supplied to the subtraction circuit 69 and fed back to the addition circuit 70 via the delay circuit 71. An output of the subtraction circuit 69 is generated at the output terminal 72.

In the fourth embodiment, hardware can be reduced by using the multiplication circuits 46 and 48 having the coefficient m as one multiplication circuit 66 in the third embodiment.

[Example 5]

6 shows a fifth embodiment of the present invention. In FIG. 6, the m sample delay circuit 82, one sample delay circuit 83, and (m-1) sample delay circuit 84 are cascaded. The input digital signal at the input terminal 81 is supplied to the subtraction circuit 85 and subtracted via the m sample delay circuit 82, one sample delay circuit 83, and (m-1) sample delay circuit 84. Supplied to the circuit 85.

The output of the connection point of the m sample delay circuit 82 and the one sample delay circuit 83 is supplied to the multiplication circuit 86 with the coefficient m. The output of the multiplication circuit 86 with the coefficient m is supplied to the addition circuit 87.

The output of the connection point of the one sample delay circuit 83 and the m sample delay circuit 84 is supplied to the multiplication circuit 88. The output of the multiplication circuit 88 of approximately m is supplied to the addition circuit 87.

The output of the addition circuit 87 is supplied to the one sample delay circuit 93.

The output of the one sample delay circuit 93 is supplied to the subtraction circuit 89. The output of the subtraction circuit 85 is supplied to the one sample delay circuit 94. The output of the one sample delay circuit 94 is supplied to the adder circuit 90. The output of the addition circuit 90 is supplied to the subtraction circuit 89 via the one sample delay circuit 91 and returned to the addition circuit 90. An output of the subtraction circuit 89 is generated at the output terminal 92.

In the third embodiment shown in FIG. 3, the fifth embodiment includes a register for latching the output of the adder circuit 50 and a delay circuit for delaying the output of the adder circuit 50 by one sample. ), The hardware is simplified.

Sixth Embodiment

7 shows a sixth embodiment of the present invention. In FIG. 7, the m sample delay circuit 102, one sample delay circuit 103, and (m-1) sample delay circuit 104 are cascaded. The input digital signal at the input terminal 101 is supplied to the subtraction circuit 105 and subtracted via the m sample delay circuit 102, one sample delay circuit 103, and (m-1) sample delay circuit 104. Supplied to the circuit 105.

The output of the connection point of the m sample delay circuit 102 and the one sample delay circuit 103 is supplied to the addition circuit 107. The output of the connection point of the one sample delay circuit 103 and the sample delay circuit 104 (m-1) is supplied to the addition circuit 107. The output of the addition circuit 107 is supplied to the multiplication circuit 106 of the coefficient m. The output of the multiplication circuit 106 is supplied to the one sample delay circuit 113. The output of the one sample delay circuit 113 is supplied to the subtraction circuit 109.

The output of the subtraction circuit 105 is supplied to the one sample delay circuit 101. The output of the one sample delay circuit 101 is supplied to the subtraction circuit 110. The output of the addition circuit 110 is supplied to the one sample delay circuit 111. The output of the one sample delay circuit 111 is supplied to the subtraction circuit 109 and returned to the addition circuit 110. An output of the subtraction circuit 109 is generated at the output terminal 112.

In the fourth embodiment shown in FIG. 5, the sixth embodiment includes a register for latching the output of the adding circuit 110 and a delay circuit for delaying the output of the adding circuit 110 by one sample. ), The hardware is simplified.

According to the present invention, it is possible to realize a high pass filter having a steep characteristic based on the commonization of the delay circuit and the counting circuit, and the averaging digital low pass filter.

Claims (3)

The input signal delayed through the cascade connection of the delay circuit of m samples and the delay circuit of (m + 1) samples, the input signal, and the delay circuit of the m samples, and the delay circuit of (m + 1) samples A first subtracting circuit to subtract, a coefficient 2m multiplying circuit that multiplies a coefficient 2m by an output signal at a connection point of the delay circuit of the m sample and the delay circuit of the (m + 1) sample, and the delay circuit of the m sample; A first addition circuit that adds an output signal at the connection point of the delay circuit of the (m + 1) sample and an output signal of the coefficient 2m multiplication circuit, and delays the output signal by one sample to return the first subtraction; Subtracting the first one sample delay circuit and the second adding circuit, the output signal of the first adding circuit and the output signal of the second adding circuit, which are added to the output signal of the circuit, and obtaining an output signal from the output unit. Having second subtraction society Digital high-pass filter as claimed. The input signal delayed through the cascade connection of the delay circuit of m samples and the delay circuit of (m + 1) samples, the input signal, and the delay circuit of the m samples, and the delay circuit of (m + 1) samples An output signal at a connection point of a third subtracting circuit to subtract, a second sample delay circuit latching an output signal of the third subtracting circuit, a delay circuit of the m samples, and a delay circuit of the (m + 1) samples A third that adds an output signal at a connection point of a coefficient 2m multiplication circuit that multiplies a coefficient by 2m, a delay circuit of the m samples, a delay circuit of the (m + 1) sample, and an output signal of the coefficient 2m multiplication circuit An addition circuit, a third one-sample delay circuit for latching the output signal of the third addition circuit, and a delay of the output signal by one sample to be fed back, and added with the output signal of the second one-sample delay circuit. Fourth one-sample delay circuit and third And a fourth subtracting circuit which subtracts the output signal of the fourth one-sample delay circuit and the output signal of the third one-sample delay circuit, and obtains an output signal at the output unit. High pass filter. (m-1) Low speed at the connection point of the sample delay circuit, the fifth one sample delay circuit and the m sample delay circuit, and the connection point of the (m-1) sample delay circuit and the fifth sample delay circuit A first coefficient m multiplier circuit, a second coefficient m multiplier circuit connected to a connection point of the fifth sample delay circuit and the delay circuit of the m samples, an input signal, and the (m-1) sample A fifth subtraction circuit for subtracting the delayed input signal through the delay circuit, the fifth one sample delay circuit and the m sample delay circuit, and the output signal of the first coefficient m multiplication circuit and the second coefficient m multiplication circuit. A fifth adding circuit for adding an output signal, a sixth sample delay circuit for adding an output signal of the fifth subtracting circuit, and a sixth adding circuit for adding the output signal to the fifth subtracting circuit; Of the output signal of the addition circuit of 5 and the sixth addition circuit And subtracting the output signal, comprising the digital subtraction circuit of claim 6 which is obtained an output signal at the output of the high pass filter.

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