KR980006275A - Bit line of semiconductor device and manufacturing method thereof - Google Patents

Bit line of semiconductor device and manufacturing method thereof Download PDF

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Publication number
KR980006275A
KR980006275A KR1019960023261A KR19960023261A KR980006275A KR 980006275 A KR980006275 A KR 980006275A KR 1019960023261 A KR1019960023261 A KR 1019960023261A KR 19960023261 A KR19960023261 A KR 19960023261A KR 980006275 A KR980006275 A KR 980006275A
Authority
KR
South Korea
Prior art keywords
bit line
tin
semiconductor device
cvd
deposited
Prior art date
Application number
KR1019960023261A
Other languages
Korean (ko)
Inventor
이상협
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960023261A priority Critical patent/KR980006275A/en
Priority to US08/863,148 priority patent/US6087259A/en
Priority to JP9149488A priority patent/JP2908774B2/en
Publication of KR980006275A publication Critical patent/KR980006275A/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Abstract

본 발명은 반도체 소자의 비트라인 및 그 제조방법에 관한 것으로, 비트라인을 비저항이 낮은 텅스텐을 사용하여 신호전달 속도를 증가시켜 소자의 성능 및 신뢰성을 향상시키도록 하기 위하여 틀랜지스터의 소오스/드레인용 확산영역에 접속되는 비트라인이 Ti, CVD-TiN, CVD-W 및 TiN의 적층 구조로 형성하는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit line of a semiconductor device and a method of manufacturing the same. In order to improve the performance and reliability of the device by increasing the signal transfer speed using tungsten having a low resistivity, the source / drain of the transistor is improved. The bit lines connected to the reference diffusion region are formed in a stacked structure of Ti, CVD-TiN, CVD-W, and TiN.

Description

반도체 소자의 비트라인 및 그 제조방법Bit line of semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 1도는 본 발명의 실시예에 의해 반도체소자의 비트라인을 제조한 것을 도시한 단면도1 is a cross-sectional view showing the manufacture of a bit line of a semiconductor device according to an embodiment of the present invention

Claims (12)

반도체 소자의 비트라인에 있어서, 트랜지스터의 소오스/드레인용 확산영역에 접속되는 비트라인이 Ti, CVD-TiN, CVD-W 및 TiN의 적층 구조로 이루어지는 것을 특징으로 하는 반도체소자의 비트라인A bit line of a semiconductor device, wherein the bit line connected to the source / drain diffusion region of the transistor has a stacked structure of Ti, CVD-TiN, CVD-W, and TiN. 제1항에 있어서, 상기 Ti는 50-1000Å의 두께로 증착된 것을 특징으로 하는 반도체소자의 비트라인The bit line of claim 1, wherein the Ti is deposited to a thickness of about 50 to about 1000 microns. 제1항에 있어서, 상기 MOCVD-TiN은 100-1000Å의 두께로 증착된 것을 특징으로 하는 반도체소자의 비트라인The bit line of a semiconductor device according to claim 1, wherein the MOCVD-TiN is deposited to a thickness of 100-1000 Å. 제1항에 있어서, 상기 CVD-W은 500-1000Å의 두께로 증착된 것을 특징으로 하는 반도체소자의 비트라인2. The bit line of a semiconductor device according to claim 1, wherein the CVD-W is deposited to a thickness of 500 to 1000 microseconds. 제1항에 있어서, 상기 TiN은 ARC(Anti-reflection coating)층으로 100-1000Å의 두께로 증착된 것을 특징으로 하는 반도체소자의 비트라인The bit line of claim 1, wherein the TiN is deposited with an anti-reflection coating (ARC) layer having a thickness of 100-1000 μs. 반도체소자의 비트라인 제조방법에 있어서, 트랜지스터의 소오스/드레인용 확산영역이 오픈되는 콘택홀을 형성한 다음, Ti, MOCVD-TiN, CVD-W 및 TiN이 적층 구조로 적층하고, 비트라인 마스크를 이용한 식각공정으로 TiN, CVD-W, CVD-TiN 및 Ti을 순차적으로 식각하여 비트라인 패턴을 형성하는 것을 특징으로 하는 반도체소자의 비트라인 제조방법In the method of manufacturing a bit line of a semiconductor device, after forming a contact hole in which a source / drain diffusion region of a transistor is opened, Ti, MOCVD-TiN, CVD-W, and TiN are stacked in a stacked structure, and a bit line mask is formed. A method for manufacturing a bit line of a semiconductor device, comprising forming a bit line pattern by sequentially etching TiN, CVD-W, CVD-TiN, and Ti by an etching process using the same. 제6항에 있어서, 상기 Ti는 50-1000Å의 두계로 증착하며, 스퍼터 방법으로 증착하는 것을 특징으로 하는 반도체소자의 비트라인 제조방법The method of claim 6, wherein the Ti is deposited at a thickness of 50-1000 μs, and is deposited by a sputtering method. 제6항에 있어서, 상기 TiN은 TDMAT를 원료로 사용하여 100-1000Å의 두께로 MOCVD방법을 이용하여 중착하는 것을 특징으로 하는 반도체소자의 비트라인 제조방법The method of manufacturing a bit line of a semiconductor device according to claim 6, wherein the TiN is deposited by using a MOCVD method with a thickness of 100-1000 GPa using TDMAT as a raw material. 제6항에 있어서, 상기 CVD-W은를 원료로 사용한 CVD 방법으로 500-5000Å의 두께로 증착하는 것을 특징으로 하는 반도체소자의 비트라인 제조방법The method of claim 6, wherein the CVD-W Method of manufacturing a bit line of a semiconductor device, characterized in that the deposition to a thickness of 500-5000Å by the CVD method using 제6항에 있어서, 상기 TiN은 스터퍼 방법에 의해 100-1000Å의 두께로 증착하는 것을 특징으로 하는 반도체소자의 비트라인 제조방법The method of claim 6, wherein the TiN is deposited by a stuffer method to a thickness of about 100 to about 1000 microns. 제6항에 있어서,상기 비트라인 패턴을 형성한 다음, 비트라인 측벽에 노출된 W이 산화되는 것을 방지하기 위하여 실리콘 산화막을 저온에서 증착하는 것을 특징으로 하는 반도체소자의 비트라인 제조방법The method of claim 6, wherein after forming the bit line pattern, a silicon oxide layer is deposited at a low temperature to prevent oxidation of W exposed on the sidewalls of the bit line. 제11항에 있어서,상기 실리콘 산화막은를 사용하여 플라즈마 CVD 방법으로 300-3000Å의 두께로 형성하는 것을 특징으로 하는 반도체소자의 비트라인 제조방법The method of claim 11, wherein the silicon oxide film is Using a plasma CVD method to form a bit line of the semiconductor device, characterized in that formed in a thickness of 300-3000CVD
KR1019960023261A 1996-06-24 1996-06-24 Bit line of semiconductor device and manufacturing method thereof KR980006275A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019960023261A KR980006275A (en) 1996-06-24 1996-06-24 Bit line of semiconductor device and manufacturing method thereof
US08/863,148 US6087259A (en) 1996-06-24 1997-05-27 Method for forming bit lines of semiconductor devices
JP9149488A JP2908774B2 (en) 1996-06-24 1997-06-06 Bit line of semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960023261A KR980006275A (en) 1996-06-24 1996-06-24 Bit line of semiconductor device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
KR980006275A true KR980006275A (en) 1998-03-30

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960023261A KR980006275A (en) 1996-06-24 1996-06-24 Bit line of semiconductor device and manufacturing method thereof

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KR (1) KR980006275A (en)

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