KR980006096A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
KR980006096A
KR980006096A KR1019960025790A KR19960025790A KR980006096A KR 980006096 A KR980006096 A KR 980006096A KR 1019960025790 A KR1019960025790 A KR 1019960025790A KR 19960025790 A KR19960025790 A KR 19960025790A KR 980006096 A KR980006096 A KR 980006096A
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KR
South Korea
Prior art keywords
film
semiconductor device
cell region
charge storage
forming
Prior art date
Application number
KR1019960025790A
Other languages
Korean (ko)
Inventor
김윤장
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960025790A priority Critical patent/KR980006096A/en
Publication of KR980006096A publication Critical patent/KR980006096A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Abstract

본 발명은 반도체소자 및 그 제조방법에 관한 것으로서, 셀영역과 주변회로 영역간에 하부 구조물의 단차에 의해 평탄화막의 경사를 원만하게 하기 위하여 셀영역의 에지 부분에 형성되는 더미셀의 캐패시터를 셀영역의 캐패시터보다 낮게 형성하여 셀영역과 주변회로 영역간의 단차에 의한 평탄화막의 경사를 원만하게 하여 경사면에 의해 발생될 수 있는 나칭 등의 패턴 불량을 방지하고, 후속 평탄화 공정을 용이하게 하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있다.The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device, The capacitor can be formed lower than the capacitor to smooth the inclination of the planarization film due to the difference in level between the cell region and the peripheral circuit region, thereby preventing a pattern defect such as hatching that may be caused by the inclined plane, facilitating the subsequent planarization process, It is possible to improve the reliability.

Description

반도체 소자 및 그 제조방법Semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 본 발명에 사용되는 반도체소자의 단면도.FIG. 2 is a cross-sectional view of a semiconductor device used in the present invention; FIG.

Claims (9)

소자분리 산화막과 모스 전계효과 트랜지스터와 캐패시터를 구비하는 셀영역과 주변회로 영역으로 구성되는 반도체 소자에 있어서, 상기 셀영역 에지 부분에 형성되어 있는 더미셀의 캐패시터를 셀영역의 캐패시터 보다 낮게 형성하여 상기 구조의 전표면에 형성되어 있는 평탄화막의 셀영역과 주변회로 영역간의 경계부분의 경사를 원만하게 하는 반도체 소자.A semiconductor device comprising a cell region including a device isolation oxide film, a MOS field effect transistor and a capacitor, and a peripheral circuit region, characterized in that a dummy cell capacitor formed at an edge portion of the cell region is formed lower than a capacitor of the cell region, And the inclination of the boundary portion between the cell region of the planarization film and the peripheral circuit region formed on the entire surface of the structure is made smooth. 제1항에 있어서, 상기 평탄화막이 BPSG나 PSG 또는 TEOS 중 어느 하나로 형성되는 것을 특징으로하는 반도체 소자.The semiconductor device according to claim 1, wherein the planarizing film is formed of BPSG, PSG, or TEOS. 제1항에 있어서, 상기 평탄화막이 별도의 층간절연막을 하부에 구비하여 수분이나 불순물의 확산을 방지하는 것을 특징으로하는 반도체 소자.The semiconductor device according to claim 1, wherein the planarizing film has a separate interlayer insulating film at the bottom to prevent diffusion of moisture or impurities. 제1항에 있어서, 상기 평탄화막 상부에는 식각 손상을 방지하기 위한 별도의 식각장벽층이 형성되어 있는 것을 특징으로하는 반도체 소자.The semiconductor device according to claim 1, wherein a separate etching barrier layer is formed on the planarizing film to prevent etching damage. 제4항에 있어서, 상기 식각장벽층이 질화막인 것을 특징으로하는 반도체 소자.The semiconductor device according to claim 4, wherein the etching barrier layer is a nitride film. 셀영역과 주변회로 영역으로 구분되어 있는 반도체기판상에 전하저장전극용 콘택홀을 구비하는 제1평탄화막을 형성하는 공정과, 상기 콘택홀을 통하여 반도체 기판과 접촉되는 전하저장전극을 형성하되, 상기 셀영역 에지부분에 형성되는 전하저장전극을 셀영역에 형성되는 전하저장전극 보다 낮게 형성하는 공정과, 상기 전하저장전극의 표면에 유전체막을 형성하는 공정과, 상기 유전체막을 감싸는 플레이트 전극을 형성하여 캐패시터를 완성하되, 상기 더미셀의 주변회로 영역측 캐패시터는 일부가 제거되도록 형성하는 공정과, 상기 구조의 전표면에 제2평탄화막을 형성하는 공정을 구비하는 반도체소자의 제조방법.Forming a first planarization film having a contact hole for a charge storage electrode on a semiconductor substrate divided into a cell region and a peripheral circuit region; forming a charge storage electrode in contact with the semiconductor substrate through the contact hole, Forming a charge storage electrode formed at an edge of a cell region to be lower than a charge storage electrode formed in a cell region; forming a dielectric film on a surface of the charge storage electrode; forming a plate electrode surrounding the dielectric film, And forming a second planarizing film on the entire surface of the structure, wherein the second planarizing film is formed on the entire surface of the structure. 제6항에 있어서, 상기 전하저장전극과 플레이트 전극이 다결정 또는 비정질 실리콘으로 형성되어 있는 것을 특징으로하는 반도체소자.The semiconductor device according to claim 6, wherein the charge storage electrode and the plate electrode are formed of polycrystalline or amorphous silicon. 제6항에 있어서, 상기 유전체막은 산화막, 질화막, 산화막-질화막-산화막의 적층막, Ta2O5, TiO2또는 SrTiO3등으로 이루어지는 군에서 임의로 선택되는 하나의 물질로 형성하는 것을 특징으로하는 반도체 소자.The dielectric film according to claim 6, wherein the dielectric film is formed of one material selected from the group consisting of an oxide film, a nitride film, a laminated film of an oxide film-nitride film-oxide film, Ta 2 O 5 , TiO 2 , SrTiO 3 , Semiconductor device. 제6항에 있어서, 상기 플레이트 전극이 500~3000Å 두께로 형성되는 것을 특징으로하는 반도체소자.The semiconductor device according to claim 6, wherein the plate electrode is formed to a thickness of 500 to 3000 ANGSTROM. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960025790A 1996-06-29 1996-06-29 Semiconductor device and manufacturing method thereof KR980006096A (en)

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