KR980005843A - Method for forming interlayer insulating film of semiconductor device - Google Patents

Method for forming interlayer insulating film of semiconductor device Download PDF

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Publication number
KR980005843A
KR980005843A KR1019960025930A KR19960025930A KR980005843A KR 980005843 A KR980005843 A KR 980005843A KR 1019960025930 A KR1019960025930 A KR 1019960025930A KR 19960025930 A KR19960025930 A KR 19960025930A KR 980005843 A KR980005843 A KR 980005843A
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South Korea
Prior art keywords
layer
forming
buffer layer
semiconductor device
insulating film
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KR1019960025930A
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Korean (ko)
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KR100213208B1 (en
Inventor
이주범
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김광호
삼성전자 주식회사
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Priority to KR1019960025930A priority Critical patent/KR100213208B1/en
Publication of KR980005843A publication Critical patent/KR980005843A/en
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Publication of KR100213208B1 publication Critical patent/KR100213208B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium

Abstract

본 발명은 메탈층사이를 절연시킬 수 있는 반도체 장치의 층간 절연막 형성 방법에 관하여 기재하고 있다. 이는, 실리콘 기판상에 도전성 물질을 소정 두께로 증착시켜서 메탈층을 형성시키는 단계와, 상기 메탈층상에 버퍼층을 형성시키는 단계와, 상기 버퍼층상에 캡핑층을 형성시키는 단계와, 상기 캡핑층상에 층간 절연막을 형성시키는 단계로 이루어진다. 따라서, 본 발명에 따르면, 메탈층과 캡핑층사이에 열응력을 완화시킬 수 있는 버퍼층을 형성시킴으로서 상기 메탈층과 캡핑층사이의 열팽창율 차이에 의한 스트레스 발생을 방지시켜서 상기 층간 절연막에 크랙이 발생시키는 것을 방지시켜 반도체 장치의 성능 및 신뢰도를 향상시킬 수 있다.The present invention describes a method of forming an interlayer insulating film of a semiconductor device capable of insulating between metal layers. The method includes depositing a conductive material to a predetermined thickness on a silicon substrate to form a metal layer, forming a buffer layer on the metal layer, forming a capping layer on the buffer layer, Thereby forming an insulating film. Therefore, according to the present invention, by forming a buffer layer between the metal layer and the capping layer to mitigate thermal stress, stress caused by a difference in thermal expansion coefficient between the metal layer and the capping layer is prevented, It is possible to improve the performance and reliability of the semiconductor device.

Description

반도체 장치의 층간 절연막 형성 방법Method for forming interlayer insulating film of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도 및 제3도는 본 발명에 따라서 층간 절연막이 형성된 실리콘 기판을 도시한 단면도.FIGS. 2 and 3 are cross-sectional views showing a silicon substrate on which an interlayer insulating film is formed according to the present invention. FIG.

Claims (9)

실리콘 기판상에 도전성 물질을 소정 두께로 증착시켜서 메탈층을 형성시키는 단계와, 상기 메탈층상에 버퍼층을 형성시키는 단계와, 상기 버퍼층상에 캡핑층을 형성시키는 단계와, 상기 캠핑층상에서 층간 절연막을 형성시키는 단계로 이루어진 것을 특징으로 하는 반도체 장치의 층간 절연막 형성 방법.A method for manufacturing a semiconductor device, comprising: forming a metal layer by depositing a conductive material on a silicon substrate to a predetermined thickness; forming a buffer layer on the metal layer; forming a capping layer on the buffer layer; And forming an interlayer insulating film on the semiconductor substrate. 제1항에 있어서, 상기 버퍼층은 산화물로 이루어져 있는 것을 특징으로 하는 반도체 장치의 층간 절연막 형성 방법.The method of claim 1, wherein the buffer layer is made of oxide. 제2항에 있어서, 상기 버퍼층은 알루미나로 이루어져 있는 것을 특징으로 하는 반도체 장치의 층간 절연막 형성 방법.3. The method according to claim 2, wherein the buffer layer is made of alumina. 제3항에 있어서, 상기 버퍼층은 플라즈마 공정에 의하여 형성되는 것을 특징으로 하는 반도체 장치의 층간 절연막 형성 방법.The method according to claim 3, wherein the buffer layer is formed by a plasma process. 제3항에 있어서, 상기 버퍼층은 O3-U 공정에 의하여 형성되는 것을 특징으로 하는 반도체 장치의 층간 절연막 형성 방법.The method according to claim 3, wherein the buffer layer is formed by an O 3 -U process. 제4항 또는 제5항에 있어서, 상기 버퍼층의 두께는 50Å 내지 200Å의 두께로 유지되는 것을 특징으로 하는 반도체 장치의 층간 절연막 형성 방법.The method according to claim 4 or 5, wherein the buffer layer is maintained at a thickness of 50 to 200 ANGSTROM. 제1항에 있어서, 상기 메탈층은 알루미늄으로 이루어져 있는 것을 특징으로 하는 반도체 장치의 층간 절연막 형성 방법.The method of claim 1, wherein the metal layer is made of aluminum. 제7항에 있어서, 상기 캡핑층은 티타늄 질화물로 이루어져 있는 것을 특징으로 하는 반도체 장치의 층간 절연막 형성 방법.8. The method of claim 7, wherein the capping layer is formed of titanium nitride. 제8항에 있어서, 상기 층간 절연막은 O3-TEOS USG로 이루어져 있는 것을 특징으로 하는 반도체 장치의 층간 절연막 형성 방법.The method according to claim 8, wherein the interlayer insulating layer is made of O 3 -TEOS USG. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960025930A 1996-06-29 1996-06-29 Method of forming isolation layer of semiconductor device KR100213208B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960025930A KR100213208B1 (en) 1996-06-29 1996-06-29 Method of forming isolation layer of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960025930A KR100213208B1 (en) 1996-06-29 1996-06-29 Method of forming isolation layer of semiconductor device

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KR980005843A true KR980005843A (en) 1998-03-30
KR100213208B1 KR100213208B1 (en) 1999-08-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001060041A1 (en) * 2000-02-14 2001-08-16 Moneyphone Co., Ltd. Multi-function telephone used by internet and pstn

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001060041A1 (en) * 2000-02-14 2001-08-16 Moneyphone Co., Ltd. Multi-function telephone used by internet and pstn

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