KR980005465A - Contact hole formation method of semiconductor device - Google Patents

Contact hole formation method of semiconductor device Download PDF

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Publication number
KR980005465A
KR980005465A KR1019960022880A KR19960022880A KR980005465A KR 980005465 A KR980005465 A KR 980005465A KR 1019960022880 A KR1019960022880 A KR 1019960022880A KR 19960022880 A KR19960022880 A KR 19960022880A KR 980005465 A KR980005465 A KR 980005465A
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South Korea
Prior art keywords
buffer layer
contact
contact buffer
forming
layer
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KR1019960022880A
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Korean (ko)
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KR100403353B1 (en
Inventor
이희기
이영춘
김상철
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김주용
현대전자산업주식회사
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Priority to KR1019960022880A priority Critical patent/KR100403353B1/en
Publication of KR980005465A publication Critical patent/KR980005465A/en
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Publication of KR100403353B1 publication Critical patent/KR100403353B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 개선된 콘택홀의 형성방법에 개시된다. 개시된 본 발명은 필드 산화막이 구비된 반도체 기판에 게이트 산화막을 형성하는 단계; 게이트 산화막 상부에 게이트 전극 물질을 증착하는 단계; 게이트 전극 물질을 소정 부분 식각하여 게이트 전극 및 콘택 예정 영역 상부에 콘택 버퍼층을 형성하는 단계; 게이트 전극과 콘택 버퍼층의 양측 기판 영역에 접합 영역용 불순물을 이온 주입하는 단계; 결과물 상부에 절연막을 증착하는 단계; 콘택 버퍼층이 노출되도록 제1콘택홀을 형성하는 단계; 콘택 버퍼층 및 게이트 산화막을 제거하여 제2콘택홀을 형성하는 단계; 및 노출된 반도체 기판에 접합 영역용 불순물을 이온 주입하는 단계를 포함하는 것을 특징으로 한다.The present invention discloses an improved method of forming a contact hole. The disclosed invention comprises the steps of forming a gate oxide film on a semiconductor substrate provided with a field oxide film; Depositing a gate electrode material over the gate oxide film; Etching a portion of the gate electrode material to form a contact buffer layer over the gate electrode and the contact planar region; Implanting impurities for the junction region into both substrate regions of the gate electrode and the contact buffer layer; Depositing an insulating film on top of the result; Forming a first contact hole to expose the contact buffer layer; Removing the contact buffer layer and the gate oxide layer to form a second contact hole; And ion implanting impurities for the junction region into the exposed semiconductor substrate.

Description

반도체 소자의 콘택홀 형성방법Contact hole formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 반도체 소자의 평면도.2 is a plan view of a semiconductor device according to the present invention.

Claims (8)

필드 산화막이 구비된 반도체 기판에 게이트 산화막을 형성하는 단계; 상기 게이트 산화막 상부에 게이트 전극 물질을 증착하는 단계; 게이트 전극 물질을 소정 부분 식각하여 게이트 전극 및 콘택 예정 영역 상부에 콘택 버퍼층을 형성하는 단계; 상기 게이트 전극과 콘택 버퍼층의 양측 기판 영역에 접합 영역용 불순물을 이온 주입하는 단계; 결과물 상부에 절연막을 증착하는 단계; 상기 콘택 버퍼층이 노출되도록 제1의 콘택홀을 형성하는 단계; 상기 콘택 버퍼층 및 콘택 버퍼층 하부에 게이트산화막을 제거하는 단계; 및 노출된 반도체 기판에 접합 영역용 불순물을 이온 주입하여 제2의 콘택홀을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.Forming a gate oxide film on a semiconductor substrate provided with a field oxide film; Depositing a gate electrode material on the gate oxide layer; Etching a portion of the gate electrode material to form a contact buffer layer over the gate electrode and the contact planar region; Ion implanting impurities for junction regions into both substrate regions of the gate electrode and the contact buffer layer; Depositing an insulating film on top of the result; Forming a first contact hole to expose the contact buffer layer; Removing a gate oxide layer under the contact buffer layer and the contact buffer layer; And forming a second contact hole by ion implanting impurities for the junction region into the exposed semiconductor substrate. 제1항에 있어서, 상기 콘택 버퍼층의 폭은 상기 제1콘택홀의 구경보다 넓은 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The method of claim 1, wherein a width of the contact buffer layer is wider than a diameter of the first contact hole. 제1항에 있어서, 상기 콘택 버퍼층은 습식 식각 방식에 의하여 제거하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The method of claim 1, wherein the contact buffer layer is removed by a wet etching method. 제1항에 있어서, 상기 절연막은 산화막과 하나 이상의 평탄화막이 교대로 증착된 막인 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The method of claim 1, wherein the insulating layer is a film in which an oxide layer and one or more planarization layers are alternately deposited. 필드 산화막 및 게이트 산화막이 구비된 반도체 기판에 게이트 전극과 소오스 전극 예정 영역에 콘택 버퍼층을 형성하는 단계; 상기 게이트 전극과 콘택 버퍼층의 양옆에 제1소오스 및 드레인 영역을 형성하는 단계; 결과물 상부에 제1절연막을 증착하는 단계; 상기 드레인 영역이 노출되도록 제1절연막을 식각하는 단계; 노출된드레인 영역에 비트 라인을 형성하는 단계; 상기 구조물 상부에 제2절연막을 증착하는 단계; 상기 콘택 버퍼층이 노출되도록 제2및 제1절연막을 식각하여 제1콘택홀 형성하는 단계; 상기 콘택 버퍼층 및콘택 버퍼층 하부의 게이트 산화막을 제거하는 단계; 및 상기 게이트 산화막이 제거된 기판에 불순물을 이온주입하여 제2소오스 영역을 구축하여 스토리지 노드 콘택홀을 형성하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.Forming a contact buffer layer on a predetermined region of the gate electrode and the source electrode on the semiconductor substrate including the field oxide film and the gate oxide film; Forming first source and drain regions on both sides of the gate electrode and the contact buffer layer; Depositing a first insulating layer on the result; Etching the first insulating layer to expose the drain region; Forming a bit line in the exposed drain region; Depositing a second insulating film on the structure; Etching the second and first insulating layers to expose the contact buffer layer to form a first contact hole; Removing the contact buffer layer and the gate oxide layer under the contact buffer layer; And forming a second node region by implanting impurities into the substrate from which the gate oxide layer has been removed to form a storage node contact hole. 제5항에 있어서, 상기 콘택 버퍼층의 폭은 상기 제1콘택홀의 구경보다 넓은 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The method of claim 5, wherein a width of the contact buffer layer is wider than a diameter of the first contact hole. 제5항에 있어서, 상기 콘택 버퍼층은 습식 식각 방식에 의하여 제거하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The method of claim 5, wherein the contact buffer layer is removed by a wet etching method. 제5항에 있어서, 상기 제1절연막과 제2절연막은 산화막과, 평탄화막 및 산화막이 교대로 적층된 막인 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.6. The method of claim 5, wherein the first insulating film and the second insulating film are formed by alternately stacking an oxide film, a planarization film, and an oxide film. ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is to be disclosed based on the initial application.
KR1019960022880A 1996-06-21 1996-06-21 Method for forming contact hole of semiconductor device KR100403353B1 (en)

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KR1019960022880A KR100403353B1 (en) 1996-06-21 1996-06-21 Method for forming contact hole of semiconductor device

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Application Number Priority Date Filing Date Title
KR1019960022880A KR100403353B1 (en) 1996-06-21 1996-06-21 Method for forming contact hole of semiconductor device

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KR980005465A true KR980005465A (en) 1998-03-30
KR100403353B1 KR100403353B1 (en) 2004-02-05

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