KR980003622A - MAT applications for testing equipment - Google Patents

Abstract

Disclosed are mating applications for testing equipment to accurately measure the high or low level output, regardless of equipment specifications. A device for testing equipment, comprising: a clock input terminal for inputting a clock; A match selection signal input stage for inputting a match selection signal; A match enable signal input terminal for inputting a match enable signal; A reference voltage input terminal for inputting a predetermined reference voltage; A buffer for buffering the output signal of the equipment; A first comparator for comparing an output signal of the equipment with a reference voltage input from the reference voltage input terminal; A second comparator comparing the output signal of the equipment with a reference voltage input from the reference voltage input terminal; A first selector for turning on a signal output from the first comparator if the signal supplied from the match select signal input terminal is a logically 'high' value; A second selector for turning on the signal output from the second comparator if the signal supplied from the match select signal input terminal is logically 'low'; A logical AND gate for performing an AND operation using a signal supplied from a match enable signal input terminal as a signal output from the first or second selector as an input signal; And a third selector for turning on the signal supplied from the clock input terminal in response to the signal output from the AND. Therefore, it provides the effect of accurately measuring the level value of the high or low level output from the equipment.

Description

MAT applications for testing equipment

Since this is an open matter, no full text was included.

2 is a conceptual diagram of equipment testing according to the present invention.

FIG. 3A is a detailed view of the mat application circuit of FIG.

Claims (1)

A match application for testing equipment, comprising: a clock input terminal for inputting an external clock; A match selection signal input stage for inputting an external match selection signal; A match enable signal input terminal for inputting an external match enable signal; A reference voltage input terminal for inputting a predetermined reference voltage; A buffer for buffering the output signal of the equipment; By comparing the output signal of the equipment and the reference voltage inputted from the reference voltage input terminal, if the level of the output signal of the equipment is greater than the level of the reference voltage logically outputs a 'high' value, if the value is 'low' value A first comparator for outputting a; By comparing the output signal of the equipment and the reference voltage input from the reference voltage input terminal, if the level of the output signal of the equipment is greater than the level of the reference voltage logically outputs a 'low' value, if the value is 'high' value A second comparator for outputting a; A first selector for turning on a signal output from the first comparator if a signal supplied from the match selection signal input terminal is logically 'high'; A second selector for turning on the signal output from the second comparator if the signal supplied from the match select signal input terminal is logically 'low'; A logical AND gate for performing an AND operation using a signal output from the first selector or the second selector and a signal supplied from the match enable signal input terminal as an input signal; And a third selector for turning on the gate supplied from the clock input terminal in response to the signal output from the AND gate. ※ Note: The disclosure is based on the initial application.