KR970078012A - Buffer circuit with offset removed - Google Patents

Buffer circuit with offset removed Download PDF

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Publication number
KR970078012A
KR970078012A KR1019960018198A KR19960018198A KR970078012A KR 970078012 A KR970078012 A KR 970078012A KR 1019960018198 A KR1019960018198 A KR 1019960018198A KR 19960018198 A KR19960018198 A KR 19960018198A KR 970078012 A KR970078012 A KR 970078012A
Authority
KR
South Korea
Prior art keywords
resistor
output signal
input terminal
outputting
terminal connected
Prior art date
Application number
KR1019960018198A
Other languages
Korean (ko)
Inventor
박재진
조율호
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960018198A priority Critical patent/KR970078012A/en
Publication of KR970078012A publication Critical patent/KR970078012A/en

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Abstract

본 발명은 오프셋이 제거된 버퍼 회로를 공개한다. 그 회로는 입력신호와 제1출력신호 사이에 직렬 연결되는 제1 및 제2저항과, 제1 및 제2저항의 접점과 연결되는 음의 입력단자 및 기준 전위와 연결된 양의 입력단자를 가지고, 제1출력신호를 출력하는 제1연산 증폭기와, 제1출력신호와 제2출력신호 사이에 직렬 연결되는 제3 및 제4저항 및 제3 및 제4저항의 접점과 연결되는 임의 입력단자와 기준 전위와 연결된 양의 입력단자를 가지고, 제2출력신호를 출력하는 제2연산 증폭기를 구비하고, 제1저항과 제3저항의 곱은 제2저항과 제4저항의 곱과 같은 것을 특징으로 하고, 출력 오프셋 전압을 제거함으로써, 버퍼링된 입력전압에 해당하며, 오프셋 에러없는 신호를 출력함으로써, 정확한 버퍼링 기능을 수행하는 효과가 있다.The present invention discloses a buffer circuit with offsets removed. The circuit has a first and a second resistor connected in series between the input signal and the first output signal, a negative input terminal connected to the contacts of the first and second resistors, and a positive input terminal connected to the reference potential, A first operational amplifier for outputting a first output signal, and an arbitrary input terminal connected to a third and fourth resistor and a third and fourth resistor contact connected in series between the first output signal and the second output signal And a second operational amplifier having a positive input terminal connected to the potential and outputting a second output signal, wherein a product of the first resistor and the third resistor is the same as the product of the second resistor and the fourth resistor, By removing the output offset voltage, it corresponds to the buffered input voltage, and by outputting a signal without offset error, there is an effect of performing the correct buffering function.

Description

오프셋이 제거된 버퍼 회로Buffer circuit with offset removed

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 오프셋이 제거된 버퍼 회로의 회로도이다.2 is a circuit diagram of a buffer circuit with offset removed according to the present invention.

Claims (1)

출력 오프셋을 제거한 버퍼 회로에 있어서, 입력신호와 제1출력신호 사이에 직렬 연결되는 제1 및 제2저항과, 제1 및 제2저항의 접점과 연결되는 음의 입력단자 및 기준 전위와 연결된 양의 입력 단자를 가지고, 상기 제1출력신호를 출력하는 제1연산 증폭기; 상기 제1출력신호와 제2출력신호 사이에 직렬 연결되는 제3 및 제4저항; 및 상기 제3 및 제4저항의 접점과 연결되는 음의 입력단자와 상기 기준 전위와 연결된 양의 입력단자를 가지고, 상기 제2출력신호를 출력하는 제2연산 증폭기를 구비하고, 상기 제1저항과 상기 제3저항의 곱은 상기 제2저항과 상기 제4저항의 곱과 같은 것을 특징으로 하는 오프셋이 제거된 버퍼 회로.A buffer circuit from which an output offset is removed, the buffer circuit comprising: a first and a second resistor connected in series between an input signal and a first output signal, and a positive input terminal and a reference potential connected to a contact of the first and second resistors; A first operational amplifier having an input terminal and outputting the first output signal; Third and fourth resistors connected in series between the first output signal and the second output signal; And a second operational amplifier having a negative input terminal connected to the contacts of the third and fourth resistors and a positive input terminal connected to the reference potential, and outputting the second output signal, wherein the first resistor And the product of the third resistor is equal to the product of the second resistor and the fourth resistor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960018198A 1996-05-28 1996-05-28 Buffer circuit with offset removed KR970078012A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960018198A KR970078012A (en) 1996-05-28 1996-05-28 Buffer circuit with offset removed

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960018198A KR970078012A (en) 1996-05-28 1996-05-28 Buffer circuit with offset removed

Publications (1)

Publication Number Publication Date
KR970078012A true KR970078012A (en) 1997-12-12

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ID=66284446

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960018198A KR970078012A (en) 1996-05-28 1996-05-28 Buffer circuit with offset removed

Country Status (1)

Country Link
KR (1) KR970078012A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100386060B1 (en) * 2000-02-28 2003-06-02 미쓰비시덴키 가부시키가이샤 Buffer circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100386060B1 (en) * 2000-02-28 2003-06-02 미쓰비시덴키 가부시키가이샤 Buffer circuit

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