KR970078012A - Buffer circuit with offset removed - Google Patents
Buffer circuit with offset removed Download PDFInfo
- Publication number
- KR970078012A KR970078012A KR1019960018198A KR19960018198A KR970078012A KR 970078012 A KR970078012 A KR 970078012A KR 1019960018198 A KR1019960018198 A KR 1019960018198A KR 19960018198 A KR19960018198 A KR 19960018198A KR 970078012 A KR970078012 A KR 970078012A
- Authority
- KR
- South Korea
- Prior art keywords
- resistor
- output signal
- input terminal
- outputting
- terminal connected
- Prior art date
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- Amplifiers (AREA)
Abstract
본 발명은 오프셋이 제거된 버퍼 회로를 공개한다. 그 회로는 입력신호와 제1출력신호 사이에 직렬 연결되는 제1 및 제2저항과, 제1 및 제2저항의 접점과 연결되는 음의 입력단자 및 기준 전위와 연결된 양의 입력단자를 가지고, 제1출력신호를 출력하는 제1연산 증폭기와, 제1출력신호와 제2출력신호 사이에 직렬 연결되는 제3 및 제4저항 및 제3 및 제4저항의 접점과 연결되는 임의 입력단자와 기준 전위와 연결된 양의 입력단자를 가지고, 제2출력신호를 출력하는 제2연산 증폭기를 구비하고, 제1저항과 제3저항의 곱은 제2저항과 제4저항의 곱과 같은 것을 특징으로 하고, 출력 오프셋 전압을 제거함으로써, 버퍼링된 입력전압에 해당하며, 오프셋 에러없는 신호를 출력함으로써, 정확한 버퍼링 기능을 수행하는 효과가 있다.The present invention discloses a buffer circuit with offsets removed. The circuit has a first and a second resistor connected in series between the input signal and the first output signal, a negative input terminal connected to the contacts of the first and second resistors, and a positive input terminal connected to the reference potential, A first operational amplifier for outputting a first output signal, and an arbitrary input terminal connected to a third and fourth resistor and a third and fourth resistor contact connected in series between the first output signal and the second output signal And a second operational amplifier having a positive input terminal connected to the potential and outputting a second output signal, wherein a product of the first resistor and the third resistor is the same as the product of the second resistor and the fourth resistor, By removing the output offset voltage, it corresponds to the buffered input voltage, and by outputting a signal without offset error, there is an effect of performing the correct buffering function.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 의한 오프셋이 제거된 버퍼 회로의 회로도이다.2 is a circuit diagram of a buffer circuit with offset removed according to the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960018198A KR970078012A (en) | 1996-05-28 | 1996-05-28 | Buffer circuit with offset removed |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960018198A KR970078012A (en) | 1996-05-28 | 1996-05-28 | Buffer circuit with offset removed |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970078012A true KR970078012A (en) | 1997-12-12 |
Family
ID=66284446
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960018198A KR970078012A (en) | 1996-05-28 | 1996-05-28 | Buffer circuit with offset removed |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970078012A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100386060B1 (en) * | 2000-02-28 | 2003-06-02 | 미쓰비시덴키 가부시키가이샤 | Buffer circuit |
-
1996
- 1996-05-28 KR KR1019960018198A patent/KR970078012A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100386060B1 (en) * | 2000-02-28 | 2003-06-02 | 미쓰비시덴키 가부시키가이샤 | Buffer circuit |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WITN | Withdrawal due to no request for examination |