KR970077997A

KR970077997A - Two-phase Non-overlapping Clock Generator

Info

Publication number: KR970077997A
Application number: KR1019960014671A
Authority: KR
Inventors: 조근래
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1996-05-06
Filing date: 1996-05-06
Publication date: 1997-12-12

Abstract

본 발명은 2위상 논 오버랩핑(2-Phase Non-Overlapping) 클럭을 발생하는 2위상 논 오버랩핑 클럭 발생기에 관한 것으로, 소요되는 소자의 수를 줄이기 위한 것이다.The present invention relates to a two-phase non-overlapping clock generator for generating a two-phase non-overlapping clock, which is intended to reduce the number of elements required.

본 발명은 2위상 논 오버랩핑 클럭의 논 오버랩핑 마진에 따라 값을 결정하는 캐패시터를 지연소자로 이용하여 2위상 논 오버랩핑 클럭을 발생한다.The present invention utilizes a capacitor that determines the value according to the non-overlapping margin of the two-phase non-overlapping clock as a delay element to generate a two-phase non-overlapping clock.

따라서 본 발명은 구성 소자의 수가 줄어들고, 지연 체인의 상태와 이를 구성하는 각 인버터의 트랜지스터의 크기도 조정해야 하는 종래의 기술에 비해 캐패시터의 값과 인버터의 임계 전압만을 제어하면 되므로 간단하게 구현할 수 있는 효과가 있다.Therefore, compared to the conventional art in which the number of constituent elements is reduced and the state of the delay chain and the size of the transistors of each inverter constituting the delay chain are adjusted, only the capacitor value and the threshold voltage of the inverter need to be controlled. It is effective.

Description

Two-phase Non-overlapping Clock Generator

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3도는 본 발명에 의한 2위상 논 오버랩핑 클럭 발생기의 구성도3 is a block diagram of a two-phase non-overlapping clock generator according to the present invention;

Claims

A capacitor 28 connected to an output terminal of the first inverter 23 and a power supply Vcc; a first inverter 23 for inverting an inverted clock CLK / A non-gate 25 (N) for outputting a first 2-phase non-overlapping clock? 1 by NORing the inverted clock CLK / and the output of the second inverter 24 as input, A NAND gate 26 inverting the output of the NAND gate 26 to negatively logically multiply the inverted clock CLK / _ and the output of the second inverter 24 as inputs, And a third inverter (27) for outputting a wrapping clock (? 2).

2. The method of claim 1, wherein the capacitor (28) is determined by a non-overlapping margin of the first and second 2-phase non-overlapping clocks (? 1,? 2) .

The inverter circuit according to claim 1, further comprising: a fourth inverter (21) for inverting the applied inverted clock signal (CLK /) and inverting the output of the fourth inverter (21) And a fifth NOR gate (22) for outputting the NOR gate to the NAND gate (26).

※ Note: It is disclosed by the contents of the first application.