KR970076872A - High Density, Fast Read-Only Memory - Google Patents

Abstract

Memory cells of read-only memory are connected in parallel between adjacent bus-bit lines. The selection of the sub-bit lines is made via a logic decoder selector. The decoder contains many rows of MOSFETs connected to columns. Only one of the MOSFETs in the row between the adjacent bit line bus and the virtual ground bus can be activated and controlled by the sub-word line pack signal with other MOSFETs connected between two adjacent sub-bit lines and not conducting. have. These active mosfets in other rows are connected to a plurality of columns. One of these fire MOSFETs is superimposed on the main bit line, and the other of these active MOSFETs is superimposed on the virtual ground. When the active MOSFET is opened, the main bit line signal and the virtual signal are detected between the corresponding memory cells between two corresponding sub-bit lines.

In this configuration, the conduction of the memory cell is overlapped between the virtual ground and the main bit line via one row of MOSFETs. These rows of MOSFETs separate memory cells from the main bit line and prevent temporary deterioration of unwanted bit line signals generated by parasitic capacitances that generate air or slow down the speed.

Description

High Density, Fast Read-Only Memory

Since this is an open matter, no full text was included.

3 shows a back-to-back arrangement of memory cells according to the present invention. 4 shows a schematic plan view of the invention. FIG. 5 is an enlarged view of FIG. 4 and shows in detail a connection between a memory cell bit line and ground.

Claims (9)

A plurality of groups of memory cells arranged in a matrix of MOSFETs, with a plurality of auxiliary-bit lines, a common gate of each row connected to one of the plurality of word lines, and in each of the above groups, two adjacent The plurality of memory cells electrically connected in parallel as columns between the sub-bit lines and the main bit, which is less than half the number of said sub-bit lines in the ratio of 1: N (N is a binary number greater than 1). And a group of selector transistor switches which function as decoders for selecting one of the main bit lines for the first bit line and one of the sub-bit lines connected to one of the main bit lines. . 2. The decoder of claim 1, wherein the decoder comprises: a first sub-decoder for i-bit information comprising a first half of imetric mosfets, a second half of imetric mosfets, and a first half of j. A second sub-decoder for j-bit information including matrix matrices and second half jmetric matrices, wherein the second half jmetric matrices are the first half jmetric matrices And the second half jmetrics mosfet, wherein the first half j matrices mop are disposed between the second half j matrices mop and the second half j matrices mop The source / drain of one first half jmetrics mosfet and the second half jmetrics mosfet is the main bit line for flow to the first virtual ground. Disposed in a first direction for the signal, wherein the source / drain of the first half j-metric matrices and the second half j-metric matrices flows to the second virtual ground in a direction opposite to the first direction. And a semiconductor read-only memory, which is arranged for the adjacent main bit line signal. 2. The decoder of claim 1, wherein the decoder further comprises: a parallel row of N MOSFETs connected to a plurality of columns and an auxiliary number of each of the above rows in which the number of the active MOSFETs between the main bit line and the adjacent virtual ground line is N. With the word line signal, only one active mosfet in each of said rows of one of said groups controllable by the normal gate of said mospets, and the other said not conducting more than said active mossts One MOSFET and each of said plurality of rows closely connected between said auxiliary bit lines, wherein said active MOSFET in each of said plurality of rows is the same line of said auxiliary bit lines Each of said plurality of rows connected to a column for another active mosfet in said other row and said Time period and the active MOSFET, a read only memory semi-conductor, characterized in that comprising second active MOS Petro superimposed on said one active MOSFET and a virtual ground lines superimposed on one of said one main bit line. 4. The read-only semiconductor of claim 3, wherein the main bit line is a first metal line, the virtual ground line is a second metal line, and the first metal line and the second metal line are adjacent to each other. Memory. 5. The semiconductor read-only memory as claimed in claim 4, wherein the first metal wire and the second metal wire sometimes switch functions. 5. The semiconductor read-only memory according to claim 4, wherein the first metal wire and the second metal wire are superimposed on word lines controlled by MOSFET. 7. The metal wire for the main bit line and the metal wire for the next bit line are adjacent to each other, and the metal wire for the virtual ground for the main bit line and the metal wire for the virtual ground for the next main bit line are also adjacent to each other. The pair of lines and the pair of virtual ground lines are semiconductor read-only memory, characterized in that selectively positioned. 8. The semiconductor read-only memory according to claim 7, wherein the selection of the metal wire for the main bit line and the selection of the metal wire for the virtual ground are controlled by address left / right signals. As a memory cell, a plurality of transistor switch selectors functioning as a decoder for sensing a row of matrix matrices and on / off states of the matrix MOSFETs, and used as main bit lines and virtual ground lines, respectively, and are determined by the address left and right selectors. A read-only memory including a plurality of metal lines superimposed on the decoder, wherein the signal from the first portion of the main bit line flows to the virtual ground in the first direction, and the first portion of the main bit line; Place the first matrix MOSFET and the second matrix MOSFET in sequence between the first part of a virtual ground line, and the signal of the above-described virtual ground in the opposite direction of the first direction from the adjacent second main bit line. Second flow, position the third matrix and the fourth matrix between the metal lines. While the address left / right selector is in the first state, one of the decoders is selected, the matrix motifs of the first matrix first part of the selected decoder are sensed through one of the metal wires, Depending on the selected decoder, the matrix motifs of the third matrix motif are sensed through the other one of the metal wires while the second or fourth matrix matrix rest is resting, and the address left / right selector is selected. While in the two states, one of the decoders is selected, the matrix motifs of the first one of the second metrics of the selected decoder are sensed through one of the metal wires and according to the selected decoder, The matrix mosfets may remove the other of the metal wires as described above while the matrix mosfet of the first or third matrix is resting. How to detect the process of removing the temporary failure of the read memory adjustment to be made. ※ Note: The disclosure is based on the initial application.