KR970071261A - Scheduler for a dynamic reconfigurable uniprocessor system - Google Patents
Scheduler for a dynamic reconfigurable uniprocessor system Download PDFInfo
- Publication number
- KR970071261A KR970071261A KR1019960011282A KR19960011282A KR970071261A KR 970071261 A KR970071261 A KR 970071261A KR 1019960011282 A KR1019960011282 A KR 1019960011282A KR 19960011282 A KR19960011282 A KR 19960011282A KR 970071261 A KR970071261 A KR 970071261A
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- South Korea
- Prior art keywords
- scheduler
- task
- inheritance
- basic
- oriented
- Prior art date
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Devices For Executing Special Programs (AREA)
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
Abstract
본 발명은 동적 재구성이 가능한 단일 프로세서 시스템의 스케쥴러에 관한 것으로서, 적어도 하나 이상의 스케쥴러에 공통적으로 필요한 속성을 포함하고 있는 기본 스케쥴러 객체, 상기 기본 스케쥴러 객체의 속성을 상속받고 소속된 타스크를 포인터를 사용하여 관리하며 소정의 제한 시간 단위로 교대로 수행되는 적어도 하나 이상의 상속 스케쥴러 객체로 이루어지는 객체 지향 스케쥴러; 및 상기 객체지향 스케쥴러의 각 상속 스케쥴러 객체에 속하며 상기 상속 스케쥴러의 스케쥴링 대상이 되고, 포인터를 가지며 이중 연결구조(double linked list)로 된 적어도 하나 이상의 타스크를 포함함을 특징으로 한다.The present invention relates to a scheduler of a single processor system capable of dynamic reconfiguration, which includes a basic scheduler object including attributes required in common to at least one scheduler, a task inheriting the attributes of the basic scheduler object, An object-oriented scheduler comprising at least one inheritance scheduler object managed and alternately performed in a predetermined time unit; And at least one task belonging to each inheritance scheduler object of the object-oriented scheduler and being a scheduling target of the inheritance scheduler, having a pointer, and having a double linked list.
본 발명에 의하면 기종의 일반적인 운영체제에서의 스케쥴링 방법에 비해 단일 프로세서 시스템에서 다양한 스케쥴링 방법이 가능하다.According to the present invention, various scheduling methods are possible in a single processor system as compared to a scheduling method in a general operating system of a machine.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.
제1도는 본 발명의 구성요소 중 하나인 객체지향 타스크의 타스크 객체의 자료구조의 일실시예를 도시한 것이다, 제2도는 본 발명의 구성요소 중 하나인 객체지향 스케쥴러의 스케쥴러 객체의 자료구조의 일실시예를 도시한 것이다, 제3도는 상기 타스크와 스케쥴러의 관계를 도시한 것이다, 제4도는 시스템 내부에서 수행되는 자료구조를 개념적으로 도시한 것이다.FIG. 1 is a block diagram of a data structure of a task object of an object-oriented task according to an embodiment of the present invention. FIG. 2 is a block diagram of a data structure of a scheduler object of an object- FIG. 3 illustrates a relationship between the task and a scheduler. FIG. 4 conceptually illustrates a data structure performed in the system. As shown in FIG.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960011282A KR100287136B1 (en) | 1996-04-15 | 1996-04-15 | Scheduler of single processor system capable of dynamic reconfiguration |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960011282A KR100287136B1 (en) | 1996-04-15 | 1996-04-15 | Scheduler of single processor system capable of dynamic reconfiguration |
Publications (2)
Publication Number | Publication Date |
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KR970071261A true KR970071261A (en) | 1997-11-07 |
KR100287136B1 KR100287136B1 (en) | 2001-04-16 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019960011282A KR100287136B1 (en) | 1996-04-15 | 1996-04-15 | Scheduler of single processor system capable of dynamic reconfiguration |
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KR (1) | KR100287136B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100728899B1 (en) * | 2005-10-27 | 2007-06-15 | 한국과학기술원 | High Performance Embedded Processor with Multiple Register Sets and Hardware Context Manager |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20000055430A (en) * | 1999-02-05 | 2000-09-05 | 서평원 | Dynamic Time Assigning Method In Input Part And Output Part Of Switching System |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03122753A (en) * | 1989-10-05 | 1991-05-24 | Nec Corp | Processor control system |
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1996
- 1996-04-15 KR KR1019960011282A patent/KR100287136B1/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100728899B1 (en) * | 2005-10-27 | 2007-06-15 | 한국과학기술원 | High Performance Embedded Processor with Multiple Register Sets and Hardware Context Manager |
Also Published As
Publication number | Publication date |
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KR100287136B1 (en) | 2001-04-16 |
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