KR970060243A - Self-Test Circuit of Memory - Google Patents

Self-Test Circuit of Memory Download PDF

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Publication number
KR970060243A
KR970060243A KR1019960000840A KR19960000840A KR970060243A KR 970060243 A KR970060243 A KR 970060243A KR 1019960000840 A KR1019960000840 A KR 1019960000840A KR 19960000840 A KR19960000840 A KR 19960000840A KR 970060243 A KR970060243 A KR 970060243A
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KR
South Korea
Prior art keywords
memory
data
address
selection
counting
Prior art date
Application number
KR1019960000840A
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Korean (ko)
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KR0178005B1 (en
Inventor
김호용
김헌철
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960000840A priority Critical patent/KR0178005B1/en
Publication of KR970060243A publication Critical patent/KR970060243A/en
Application granted granted Critical
Publication of KR0178005B1 publication Critical patent/KR0178005B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/20—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

본 발명은 메모리의 자기 테스트 회로를 공개한다. 그 회로는 복수개의 메모리 셀들을 구비한 메모리, 어드레스를 단방향으로 계수하여 상기 메모리로 출력하기 위한 어드레스 계수수단, 워드 크기의 0 데이타 또는 상기 어드레스 계수수단의 출력신호중 상기 워드 크기의 데이타를 선택신호에 응답하여 선택하여 상기 메모리로 입력하기 위한 선택수단, 상기 선택신호를 발생하기 위한 제어수단, 및 상기 메모리로부터의 출력 데이타와 상기 선택수단의 출력 데이타가 일치하는지를 비교하기 위한 비교수단으로 구성되어 있다. 따라서, 구성이 간단하여 칩면적을 작게 차지할 뿐만 아니라, 자기 테스트 제어회로가 멀티플렉서의 선택단자만을 제어하여 원하는 어드레스 시퀀스를 생성할 수 있기 때문에 어드레스 크기가 변하더라도 자기 테스트 회로의 설계가 손쉬워진다.The present invention discloses a magnetic test circuit of a memory. The circuit includes a memory having a plurality of memory cells, address counting means for counting addresses in a unidirectional manner and outputting the counted data to the memory, 0 data of a word size or data of the word size among output signals of the address counting means to a selection signal And a comparison means for comparing whether the output data from the memory and the output data of the selection means coincide with each other. Therefore, the configuration is simple and not only occupies a small chip area, but also allows the magnetic test control circuit to control only the selection terminal of the multiplexer to generate the desired address sequence, thereby facilitating the design of the magnetic test circuit even if the address size is changed.

Description

메모리의 자기 테스트회로Self-Test Circuit of Memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 본 발명의 자기 테스트 회로의 블럭도이다.FIG. 2 is a block diagram of the magnetic test circuit of the present invention. FIG.

Claims (2)

복수개의 메모리 셀들을 구비한 메모리; 어드레스를 단방향으로 계수하여 상기 메모리로 출력하기 위한 어드레스 계수수단; 0 데이타 또는 상기 어드레스 계수수단의 출력신호의 각 비트 데이타를 선택신호에 응답하여 선택하여 상기 메모리로 입력하기 위한 선택수단; 상기 선택신호를 발생하기 위한 제어수단; 및 상기 메모리로부터의 출력 데이타와 상기 선택수단의 출력 데이타가 일치하는지를 비교하기 위한 비교수단을 구비한 것을 특징으로 하는 자기 테스트 제어회로.A memory having a plurality of memory cells; Address counting means for counting an address in a unidirectional manner and outputting the counted value to the memory; 0 data or each bit data of an output signal of the address counting means in response to a selection signal and inputting the bit data to the memory; Control means for generating the selection signal; And comparison means for comparing whether the output data from said memory and the output data of said selection means are coincident with each other. 복수개의 메모리 셀들을 구비한 메모리; 어드레스를 단방향으로 계수하여 상기 메모리로 출력하기 위한 어드레스 계수수단; 워드 크기의 0데이타 또는 상기 어드레스 계수수단의 출력신호중 상기 워드 크기의 데이타를 선택신호에 응답하여 선택하여 상기 메모리로 입력하기 위한 선택수단; 상기 선택신호를 발생하기 위한 제어수단; 및 상기 메모리로부터의 출력 데이타와 상기 선택수단의 출력 데이타가 일치하는지를 비교하기 위한 비교수단을 구비한 것을 특징으로 하는 자기 테스트 제어회로.A memory having a plurality of memory cells; Address counting means for counting an address in a unidirectional manner and outputting the counted value to the memory; Selection means for selecting data of a word size of 0 data or an output signal of the address count means in response to a selection signal and inputting the data of the word size into the memory; Control means for generating the selection signal; And comparison means for comparing whether the output data from said memory and the output data of said selection means are coincident with each other. ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960000840A 1996-01-17 1996-01-17 Self testing circuit of memory KR0178005B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960000840A KR0178005B1 (en) 1996-01-17 1996-01-17 Self testing circuit of memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960000840A KR0178005B1 (en) 1996-01-17 1996-01-17 Self testing circuit of memory

Publications (2)

Publication Number Publication Date
KR970060243A true KR970060243A (en) 1997-08-12
KR0178005B1 KR0178005B1 (en) 1999-04-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960000840A KR0178005B1 (en) 1996-01-17 1996-01-17 Self testing circuit of memory

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Publication number Publication date
KR0178005B1 (en) 1999-04-15

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