KR970060242A - Flash memory device - Google Patents

Flash memory device Download PDF

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Publication number
KR970060242A
KR970060242A KR1019960001661A KR19960001661A KR970060242A KR 970060242 A KR970060242 A KR 970060242A KR 1019960001661 A KR1019960001661 A KR 1019960001661A KR 19960001661 A KR19960001661 A KR 19960001661A KR 970060242 A KR970060242 A KR 970060242A
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KR
South Korea
Prior art keywords
word line
line voltage
supplied
program
memory device
Prior art date
Application number
KR1019960001661A
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Korean (ko)
Inventor
심현수
Original Assignee
김주용
현대전자산업 주식회사
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960001661A priority Critical patent/KR970060242A/en
Publication of KR970060242A publication Critical patent/KR970060242A/en

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Abstract

본 발명은 플래쉬 메모리 장치(Flash Memory device)에 관한 것으로서, 멀티레벨 셀(multi level cell) 각각의 워드라인에 각기 다른 전압을 공급하여 하나의 센스앰프로 프로그램 확인동작을 시행하도록 한 플래쉬 메모리 장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device, and more particularly, to a flash memory device in which a different voltage is supplied to each word line of a multi level cell to perform a program checking operation with a single sense amplifier .

Description

플래쉬 메모리 장치Flash memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 본 발명에 따른 플래쉬 메모리 장치의 회로도.FIG. 2 is a circuit diagram of a flash memory device according to the present invention. FIG.

제3도는 본 발명에 따른 플래쉬 메모리 장치에 있어서 워드라인의 접속관계를 도시한 회로도.FIG. 3 is a circuit diagram showing a connection relationship of word lines in the flash memory device according to the present invention; FIG.

Claims (4)

멀티레벨 셀 각각의 워드라인에 프로그램 확인 동작시 워드라인 전압 발생회로로부터 각기 다른 전압레벨을 공급하고 하나의 센스앰프로 프로그램 확인동작을 시행할 수 있도록 구성되는 것을 특징으로 하는 플래쉬 메모리 장치.Wherein the program verify operation is performed by supplying a different voltage level from the word line voltage generating circuit to the word line of each of the multi-level cells and performing a program checking operation with one sense amplifier. 제1항에 있어서, 상기 각각의 워드라인은 선택된 로우 디코더의 출력에 의해 제1 워드라인 전압은 인버터를 통해 제1 워드라인으로 공급되고, 상기 제1 워드라인 전압에 의해 통제되는 NMOS 트랜지스터는 소오스전극이 접지단자에 접속되고, 드레인전극이 저항을 통해 제2 워드라인 전압단자에 접속되며, 상기 제1 워드라인 전압에 의해 제2 워드라인 전압은 인버터를 통해 제2 워드라인으로 공급되고, 제 N-1 워드라인 전압에 의해 제N 워드라인 전압은 인버터를 통해 제N 워드라인으로 공급되도록 구성되는 것을 특징으로 하는 플래쉬 메모리 장치.2. The method of claim 1, wherein each word line is supplied by a selected row decoder output to a first word line via a first word line voltage, and an NMOS transistor controlled by the first word line voltage is supplied to a source An electrode is connected to a ground terminal and a drain electrode is connected to a second word line voltage terminal through a resistor and the second word line voltage is supplied to the second word line through the inverter by the first word line voltage, And the Nth word line voltage is supplied to the Nth word line through the inverter by an N-1 word line voltage. 제1항에 있어서, 상기 각각의 워드라인은 선택된 로우 디코더의 출력에 의해 각기 다른 워드라인 전압이 인버터를 통해 공급되도록 구성되는 것을 특징으로 하는 플래쉬 메모리 장치.2. The flash memory device of claim 1, wherein each word line is configured such that a different word line voltage is supplied via an inverter by an output of a selected row decoder. 제1항에 있어서, 상기 워드라인 전압 발생회로는 입력되는 두 입출력신호에 따라 데이타를 래치하는 래치 회로와, 프로그램 인에이블바신호에 따라 상기 래치회로에 저장된 프로그램시 워드라인 전압을 선택적으로 출력되는 PMOS 트랜지스터와, 상기 프로그램 인에이블바신호에 따라 상기 래치회로에 저장된 프로그램 확인시 워드라인 전압을 선택적으로 출력하는 NMOS 트랜지스터로 구성되는 것을 특징으로 하는 플래쉬 메모리 장치.2. The semiconductor memory device according to claim 1, wherein the word line voltage generating circuit comprises: a latch circuit for latching data according to two input / output signals inputted; and a word line voltage generator for selectively outputting a program word line voltage stored in the latch circuit according to a program enable bar signal A PMOS transistor and an NMOS transistor for selectively outputting a word line voltage upon checking a program stored in the latch circuit according to the program enable bar signal. ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960001661A 1996-01-26 1996-01-26 Flash memory device KR970060242A (en)

Priority Applications (1)

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KR1019960001661A KR970060242A (en) 1996-01-26 1996-01-26 Flash memory device

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KR1019960001661A KR970060242A (en) 1996-01-26 1996-01-26 Flash memory device

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KR970060242A true KR970060242A (en) 1997-08-12

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100680479B1 (en) * 2005-04-11 2007-02-08 주식회사 하이닉스반도체 Method for verifying successful programming non-volatile memory device
KR100684873B1 (en) * 2004-11-22 2007-02-20 삼성전자주식회사 Nonvolatile memory device and word line voltage control method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100684873B1 (en) * 2004-11-22 2007-02-20 삼성전자주식회사 Nonvolatile memory device and word line voltage control method thereof
US7423908B2 (en) 2004-11-22 2008-09-09 Samsung Electronics Co., Ltd. Nonvolatile memory devices and methods of controlling the wordline voltage of the same
US7808838B2 (en) 2004-11-22 2010-10-05 Samsung Electronics Co., Ltd. Nonvolatile memory devices and methods of controlling the wordline voltage of the same
US8085595B2 (en) 2004-11-22 2011-12-27 Samsung Electronics Co., Ltd. Nonvolatile memory devices and methods of controlling the wordline voltage of the same
KR100680479B1 (en) * 2005-04-11 2007-02-08 주식회사 하이닉스반도체 Method for verifying successful programming non-volatile memory device
US7310271B2 (en) 2005-04-11 2007-12-18 Hynix Semiconductor Inc. Program-verify method of non-volatile memory device

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