KR970059983A

KR970059983A - Image synthesizer

Info

Publication number: KR970059983A
Application number: KR1019960001963A
Authority: KR
Inventors: 이광기
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1996-01-29
Filing date: 1996-01-29
Publication date: 1997-08-12
Also published as: KR0170736B1

Abstract

본 발명은 영상합성장치에 관한 것으로서, 합성하고자 하는 N비트의 제1영상을 상위 어드레스로, M비트의 합성 가중치신호 k를 하위 어드레스로 하는 어드레스(i)를 입력하여 표1에서와 같이 해당어드레스에 저장된 값 LUIT(i)를 출력하는 LUIT(11)과, 합성하고자 하는 N비트의 제2영상을 상위 어드레스로, k의 비트 보수인 M비트의 ~k 신호를 하위 어드레스로 하는 어드레스(i)를 입력하여 표1에서와 같이 해당어드레스에 저장된 값 LUT2(i)를 출력하는 LUT2(13)과, LUT2(13)에서 출력되는 신호를 가산하기 위한 가산기(15)와, 가산기(15)에서 출력되는 신호를 어드레스(i)로 하여 표2에서와 같이 해당어드레스에 저장된 값 LUT3(i)를 출력하는 LUT3(17)로 구성된다. 따라서, 두가지 이상의 영상신호를 중첩 및 합성할때, 곱셈기를 사용하지 않고 인버터, 가산기와 룩업테이블을 이용하여 간단하게 구현할 수 있으므로 처리속도를 향상시킬 수 있다.The present invention relates to an image synthesizing apparatus, in which an address (i) in which a first image of N bits to be synthesized is an upper address and an M-bit synthesis weight signal k is a lower address is input, An address (i) for outputting a value LUIT (i) stored in an address of the second image to be synthesized, An LUT2 13 for outputting the value LUT2 (i) stored at the address as shown in Table 1, an adder 15 for adding the signal output from the LUT2 13, And a LUT 3 (17) for outputting the value LUT3 (i) stored at the address as shown in Table 2, with the signal being the address (i) Therefore, when two or more video signals are superimposed and synthesized, it can be implemented simply by using an inverter, an adder, and a lookup table without using a multiplier, thereby improving the processing speed.

Description

Image synthesizer

제1도는 본 발명에 의한 영상합성장치를 나타낸 블럭도.FIG. 1 is a block diagram showing a video synthesizing apparatus according to the present invention; FIG.

Claims

(I) = C1 * k, (where C1 = 0, 1) is input by inputting an address (i) having a first image (CI) , 2..., 2 ^N -1, k = 0, 1, 2, ..., 2 ^M -1, i = 0,1,2, ..., 2 ^{N + M} -1) A first lookup table; (I) = C2 * to k (i) by inputting an address (i) having a lower address as an upper address of the N-bit second image C2 to be synthesized and a ~ k signal of M bits , ^{(where, C2 = 0,1,2, ... 2 N} -1, ~ k = 0,1,2, ..., 2 M -1, i = 0,1,2, ..., 2 N + M -1 A second look-up table for outputting the same value as the first look-up table; An adder for adding the signals output from the first look-up table and the second look-up table; And to LUT3 (i) = a signal generated from the adder as an address (i) (i + a) / (2 N -1) ( where, i = 0,1,2, ..., 2 N + M, 0 &Lt; / = a < = 2 < ^N -2).

※ Note: It is disclosed by the contents of the first application.