KR970058752A - Command processing method - Google Patents

Command processing method Download PDF

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Publication number
KR970058752A
KR970058752A KR1019960000838A KR19960000838A KR970058752A KR 970058752 A KR970058752 A KR 970058752A KR 1019960000838 A KR1019960000838 A KR 1019960000838A KR 19960000838 A KR19960000838 A KR 19960000838A KR 970058752 A KR970058752 A KR 970058752A
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KR
South Korea
Prior art keywords
arbitrary data
instruction
data
address
storing
Prior art date
Application number
KR1019960000838A
Other languages
Korean (ko)
Other versions
KR100188018B1 (en
Inventor
정우영
Original Assignee
김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960000838A priority Critical patent/KR100188018B1/en
Publication of KR970058752A publication Critical patent/KR970058752A/en
Application granted granted Critical
Publication of KR100188018B1 publication Critical patent/KR100188018B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)

Abstract

본 발명은 명령어 처리방법을 공개한다. 그 방법은 임의의 데이타가 포함된 명령어와 임의의 데이타가 포함되지 않은 명령어 및 임의의 데이타를 저장하기 위한 페치 메모리의 명령어 처리방법에 있어서, 만일 상기 임의의 데이타가 포함된 명령어가 입력되면, 상기 페치 메모리의 제1어드레스의 명령어 저장영역에 저장하고, 상기 임의의 데이타는 상기 페치 메모리의 제1어드레스의 데이타 저장영역에 저장하고, 상기 제2어드레스의 데이타 저장영역에는 0을 저장한다. 따라서, 명령어 수행시간을 줄일 수 있다.The present invention discloses a command processing method. A method of processing instructions in a fetch memory for storing an instruction including arbitrary data, an instruction not including arbitrary data, and arbitrary data, the method comprising: if an instruction including the arbitrary data is input, Storing the arbitrary data in a data storage area of a first address of the fetch memory and storing 0 in a data storage area of the second address. Therefore, the instruction execution time can be reduced.

Description

명령어 처리방법Command processing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도는 종래의 페치 메모리의 구성을 나타내는 것이다,FIG. 1 shows a configuration of a conventional fetch memory.

제2도는 본 발명의 페치 메모리의 구조를 나타내는 것이다,FIG. 2 shows the structure of the fetch memory of the present invention.

제3도는 본 발명의 명령어 처리방법을 설명하기 위한 것이다,FIG. 3 is for explaining a command processing method of the present invention,

제4도는 제3도에 나타낸 방법의 문제점을 개선하기 위한 명령어 처리 방법을 설명하기 위한 것이다.FIG. 4 is for explaining a command processing method for improving the problem of the method shown in FIG.

Claims (2)

임의의 데이타가 포함된 명령어와 임의의 데이타가 포함되지 않은 명령어 및 임의의 데이타를 저장하기 위한 페치 메모리의 명령어 처리방법에 있어서, 만일 상기 임의의 데이타가 포함된 명령어가 입력되면, 상기 페치 메모리의 제1어드레스의 명령어 저장영역에 저장하고, 상기 임의의 데이타는 상기 페치 메모리의 제1어드레스의 데이타 저장영역에 저장하고, 만일 상기 임의의 데이타가 포함되지 않은 명령어가 입력되면, 상기 페치 메모리의 제2어드레스의 명령어 저장영역에 저장하고, 상기 제2어드레스의 데이타 저장영역에는 0을 저장하는 것을 특징으로 하는 명령어 처리방법.A method of processing a command in a fetch memory for storing an instruction including arbitrary data, an instruction not containing any data, and arbitrary data, wherein if an instruction containing the arbitrary data is input, Storing the arbitrary data in a data storage area of the first address of the fetch memory, and if an instruction not including the arbitrary data is input, 2 address in the data storage area of the second address, and 0 is stored in the data storage area of the second address. 제1항에 있어서, 상기 페치 메모리의 메모리 영역에 임의의 데이타를 포함한 명령어인지 아닌지를 표시하기 위한 체크 비트를 두는 것을 특징으로 하는 명령어 처리방법.The command processing method according to claim 1, wherein a check bit for indicating whether or not an instruction including arbitrary data is placed in a memory area of the fetch memory. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960000838A 1996-01-17 1996-01-17 Instruction process method KR100188018B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960000838A KR100188018B1 (en) 1996-01-17 1996-01-17 Instruction process method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960000838A KR100188018B1 (en) 1996-01-17 1996-01-17 Instruction process method

Publications (2)

Publication Number Publication Date
KR970058752A true KR970058752A (en) 1997-08-12
KR100188018B1 KR100188018B1 (en) 1999-06-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960000838A KR100188018B1 (en) 1996-01-17 1996-01-17 Instruction process method

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KR (1) KR100188018B1 (en)

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KR100188018B1 (en) 1999-06-01

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