KR970058095A - Fault handling device in exchange - Google Patents
Fault handling device in exchange Download PDFInfo
- Publication number
- KR970058095A KR970058095A KR1019950060984A KR19950060984A KR970058095A KR 970058095 A KR970058095 A KR 970058095A KR 1019950060984 A KR1019950060984 A KR 1019950060984A KR 19950060984 A KR19950060984 A KR 19950060984A KR 970058095 A KR970058095 A KR 970058095A
- Authority
- KR
- South Korea
- Prior art keywords
- subsystem
- processor
- exchange
- alarm
- fault
- Prior art date
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- Monitoring And Testing Of Exchanges (AREA)
Abstract
본 장치는 교환기의 서브시스템이 하나의 AACA만으로 장애처리가 이루어지도록 하기 위한 장애처리장치로서, 본 장치는 교환기의 각 서브시스템내에 구비되어 있는 디바이스; 디바이스에서 발생되는 장애를 검출하기 위한 주변프로세서; 주변프로세서에서 검출된 장애내용을 보고 받은 서브시스템 알람인터페이스; 서브시스템 내의 주변프로세서에 대한 장애발생상태를 체크하기 위한 알람액서스 제어어셈블리; 알람엑세스; 제어어셈블리에서 검출된 장애 발생상태를 보고받은 주프로세서; 주프로세서와 서브시스템 알람인터페이스로부터 전송되는 장애내용을 운용자가 인식할 수 있도록 처리하는 운용유지 보수 프로세서내의 장애처리블럭을 포함하도록 구성된다.The apparatus is a fault handling apparatus for causing the subsystem of the exchange to fail with only one AACA, the apparatus comprising: a device provided in each subsystem of the exchange; A peripheral processor for detecting a failure occurring in the device; A subsystem alarm interface that reports the fault detected by the peripheral processor; An alarm access control assembly for checking a fault condition for a peripheral processor in the subsystem; Alarm access; A main processor that reports a failure state detected by the control assembly; It is configured to include a failure handling block in the operation maintenance processor for processing an operator to recognize failures transmitted from the main processor and the subsystem alarm interface.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제3도는 교환기에 있어서 본 발명에 따른 장애처리장치의 기능블럭도,3 is a functional block diagram of a fault handling apparatus according to the present invention in an exchanger;
제4도는 제3도와 같은 구조로 이루어진 본 발명에 따른 연결망 서브시스템에 대한 장애처리장치의 구성도4 is a block diagram of a failure handling apparatus for a network subsystem according to the present invention having a structure as shown in FIG.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950060984A KR970058095A (en) | 1995-12-28 | 1995-12-28 | Fault handling device in exchange |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950060984A KR970058095A (en) | 1995-12-28 | 1995-12-28 | Fault handling device in exchange |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970058095A true KR970058095A (en) | 1997-07-31 |
Family
ID=66621375
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950060984A KR970058095A (en) | 1995-12-28 | 1995-12-28 | Fault handling device in exchange |
Country Status (1)
Country | Link |
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KR (1) | KR970058095A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100321479B1 (en) * | 1998-12-24 | 2002-05-13 | 서평원 | How to manage error collection on the exchange subprocessor |
-
1995
- 1995-12-28 KR KR1019950060984A patent/KR970058095A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100321479B1 (en) * | 1998-12-24 | 2002-05-13 | 서평원 | How to manage error collection on the exchange subprocessor |
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