KR970056360A - Asynchronous Delivery Mode Hierarchy Processing Unit - Google Patents

Asynchronous Delivery Mode Hierarchy Processing Unit Download PDF

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Publication number
KR970056360A
KR970056360A KR1019950052305A KR19950052305A KR970056360A KR 970056360 A KR970056360 A KR 970056360A KR 1019950052305 A KR1019950052305 A KR 1019950052305A KR 19950052305 A KR19950052305 A KR 19950052305A KR 970056360 A KR970056360 A KR 970056360A
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KR
South Korea
Prior art keywords
cell
receiving
switch
transmitting
out means
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KR1019950052305A
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Korean (ko)
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KR0153945B1 (en
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백정훈
최준균
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양승택
한국전자통신연구원
이준
한국전기통신공사
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Priority to KR1019950052305A priority Critical patent/KR0153945B1/en
Publication of KR970056360A publication Critical patent/KR970056360A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/104—Asynchronous transfer mode [ATM] switching fabrics
    • H04L49/105—ATM switching elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/112—Switch control, e.g. arbitration
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

본 발명은 기가급 비동기 전담로드 계층 처리 장치에 관한 것으로, 다수의 입력포트로부터 입력되는 ATM 셀을 수신하여 일괄적인 경로설정을 하여 셀 지연시간을 줄이며 정렬기켜 저장하도록 하는 셀 정렬수단; 상기 셀 정렬수단에 의해 정렬된 해당 셀을 저장하는 수신 선입선출수단; ATM 셀 스위칭을 위하여 스위치경로를 설정한 후에 상기 수신선입선출수단으로부터 셀을 읽은 후 스위치를 통하여 셀을 해다 포트로 송신하는 크로스 포인트 스위칭 수단; 상기 수신 선입선출수단이 하나 이상의 셀을 저장하고 있는 경우 상기 수신 선입선출수단으로부터 읽는 동작을 시작하며, VPI/VCI 변환을 수행하는 VPI/VCI 변화수단(Translator); 상기 VPI/VCI 변환수단(Translator)에 연결되어 다수의 입력포트로 수신되는 셀의 출력 포트가 동일한 경우에 이를 해결하는 컨텐션 해소수단(Contention Resolver); 상기 컨텐션 해소수단으로부터 각 셀에 대한 출력 포트를 수신하여 스위치의 경로를 설정하여 상기 수신 선업선출수단 및 크로스 포인트 스위칭 수단으로 제공하는 스위치 제어수단; 상기 크로스 포인트 스위칭 수단으로부터 셀 시작신호를 입력받아 읽기 신호를 전송하는 스위치 수신수단; 상기 스위치 수신수단으로부터 읽기 신호를 수신하면 즉시 셀을 수신하여 저장하는 송신 선입선출수단; 상기 송신 선입선출수단으로부터 데이타가 수신되었음을 알리는 신호를 감지하여 데이타를 읽은 후 인접가능 블럭으로 셀을 송신하는 셀 전송수단을 구비하는 것을 특징으로 한다.The present invention relates to a giga-level asynchronous dedicated load layer processing apparatus, comprising: cell aligning means for receiving an ATM cell inputted from a plurality of input ports to collectively set a path, thereby reducing cell delay time and storing the alignment; Receiving first-in, first-out means for storing the corresponding cells aligned by the cell alignment means; Cross-point switching means for reading a cell from said first-in first-out means after transmitting a switch path for ATM cell switching and transmitting the cell to a port through a switch; VPI / VCI changing means (Translator) to start the operation to read from the receiving first-in, first-out means when the receiving first-in first-out means is storing one or more cells; A contention resolver that is connected to the VPI / VCI translator and solves the case where the output ports of the cells received by the plurality of input ports are the same; Switch control means for receiving an output port for each cell from the contention release means to set a path of the switch and to provide the received first-employment means and the cross-point switching means; Switch receiving means for receiving a cell start signal from the cross point switching means and transmitting a read signal; Transmission first-in, first-out means for receiving and storing a cell immediately upon receiving a read signal from the switch receiving means; And cell transmitting means for detecting a signal indicating that data has been received from the first-in, first-out means, reading the data, and transmitting the cell to an adjacent block.

Description

비동기 전달모드 계층 처리 장치Asynchronous Delivery Mode Hierarchy Processing Unit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 구성도.1 is a block diagram of the present invention.

제2도는 셀 정렬기의 타이밍도.2 is a timing diagram of a cell aligner.

제3도는 VPI/VCI 변환기의 타이밍도.3 is a timing diagram of a VPI / VCI converter.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 셀 정렬기 2 : VPI/VCI 변환기1: cell sorter 2: VPI / VCI converter

3 : 스위치 제어기 4 : 스위치 수신기3: switch controller 4: switch receiver

5 : 셀 전송기 6 : 크로스 포인트 스위치5: cell transmitter 6: crosspoint switch

Claims (1)

다수의 입력포트로부터 입력되는 ATM 셀을 수신하여 일괄적인 경로설정을 하여 셀 지연시간을 줄이며 정렬시켜 저장하도록 하는 셀 정력수단(1); 상기 셀 정렬수단(1)에 의해 정렬된 해당 셀을 저장하는 수신 선입선출수단(7); ATM 셀 스위칭을 위하여 스위치경로를 설정한 후에 상기 수신선입선출수단(7)으로부터 셀을 읽은 후 스위치를 통하여 셀을 해당 포트로 송신하는 크로스 포인트 스위칭 수단(6); 상기 수신 선입선출수단(7)이 하나 이상의 셀을 저장하고 있는 경우 상기 수신 선입선출수단(7)으로부터 읽는 동작을 시작하며, VPI/VCI 변환을 수행하는 VPI/VCI 변환수단(Translator)(2); 상기 VPI/VCI 변환수단(Translator)(2)에 연결되어 다수의 입력포트로 수신되는 셀의 출력 포트가 동일 한 경우에 이를 해결하는 컨텐션 해소수단(Contention Resolver)(9); 상기 컨텐션 해소수단(9)으로부터 각 셀에 대한 출력 포트를 수신하여 스위치의 경로를 설정하여 상기 수신 선입선출수단(7) 및 크로스 포인트 스위칭 수단(6)으로 제공하는 스위치 제어수단(3); 상기 크로스 포인트 스위칭 수단(6)으로부터 셀 시작신호를 입력받아 읽기 신호를 전송하는 스위치 수신수단(4); 상기 스위치 수신수단(4)으로부터 읽기 신호를 수신하면 즉시 셀을 수신하여 저장하는 송신 선입선출수단(8); 상기 송신 선입선출수단(8)으로부터 데이타가 수신되었음을 알리는 신호를 감지하여 데이타를 읽은 후 인접가능 블럭으로 셀을 송신하는 셀 전송수단(5)을 구비하는 것을 특징으로 하는 비동기 전달모드 계층 처리장치.Cell energizing means (1) for receiving ATM cells input from a plurality of input ports to collectively set routing to reduce cell delay time and to align and store them; Receiving first-in, first-out means (7) for storing the corresponding cells aligned by the cell alignment means (1); Cross point switching means (6) for setting a switch path for ATM cell switching and reading the cell from the first-in, first-out means (7) and transmitting the cell to the corresponding port through the switch; VPI / VCI translator 2 which starts reading operation from the first-in first-out means 7 when the receiving first-in first-out means 7 stores one or more cells, and performs VPI / VCI conversion. ; A contention resolver (9) connected to the VPI / VCI translator (2) to solve the case where the output ports of the cells received by the plurality of input ports are the same; Switch control means (3) for receiving the output port for each cell from the contention release means (9) to set the path of the switch and to provide it to the first-in first-out means (7) and the cross point switching means (6); Switch receiving means (4) for receiving a cell start signal from the cross point switching means (6) and transmitting a read signal; Transmission first-in first-out means (8) for receiving and storing a cell immediately upon receiving a read signal from said switch receiving means (4); And cell transmitting means (5) for detecting a signal indicating that data has been received from the first-in first-out means (8), reading the data, and transmitting the cell to an adjacent block. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950052305A 1995-12-20 1995-12-20 Atm layer processing apparatus KR0153945B1 (en)

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KR1019950052305A KR0153945B1 (en) 1995-12-20 1995-12-20 Atm layer processing apparatus

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Application Number Priority Date Filing Date Title
KR1019950052305A KR0153945B1 (en) 1995-12-20 1995-12-20 Atm layer processing apparatus

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KR970056360A true KR970056360A (en) 1997-07-31
KR0153945B1 KR0153945B1 (en) 1998-11-16

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000019804A (en) * 1998-09-15 2000-04-15 윤종용 Cell delay minimizing method of partial filled non-synchronous transmitting mode adaptation layer cell

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000019804A (en) * 1998-09-15 2000-04-15 윤종용 Cell delay minimizing method of partial filled non-synchronous transmitting mode adaptation layer cell

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