KR970056175A - Spread Spectrum PN Code Tracking Device Using Parallel Correlator - Google Patents
Spread Spectrum PN Code Tracking Device Using Parallel Correlator Download PDFInfo
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- KR970056175A KR970056175A KR1019950050514A KR19950050514A KR970056175A KR 970056175 A KR970056175 A KR 970056175A KR 1019950050514 A KR1019950050514 A KR 1019950050514A KR 19950050514 A KR19950050514 A KR 19950050514A KR 970056175 A KR970056175 A KR 970056175A
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- code
- signal
- modulo
- generating
- correlation value
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- Synchronisation In Digital Transmission Systems (AREA)
- Mobile Radio Communication Systems (AREA)
Abstract
본 발명은 병렬 상관기를 이용한 대역확산 PN 코드 트랙킹장치에 관한 것으로서, 종래기술은 다경로 채널을 통과한 신호를 수신할 때 다경로의 랜덤한 시간지연으로 인한 신호의 찌그러짐 현상에 의해 수신신호의 복조시 에러를 증가시켜 전체적인 성능을 저하시켰던 문제점이 있었다.The present invention relates to a spread spectrum PN code tracking device using a parallel correlator, and the prior art demodulates a received signal due to signal distortion due to random time delay of a multipath when receiving a signal passing through a multipath channel. There was a problem that the overall performance was reduced by increasing the error.
따라서 본 발명은 수신신호를 N개의 지연 레지스터를 통과시킨 후 자체 발생된 PN 코드 타이밍과 상관값을 계산하고 적분하며, 적분된 신호를 샘플링하여 최대 상관값을 선택한다.Accordingly, the present invention calculates and integrates the PN code timing and correlation values generated after passing the received signals through the N delay registers, and selects the maximum correlation value by sampling the integrated signal.
그리고 최대 상관값을 갖는 시점을 기준으로 모듈로 N 계수기를 리셋시키고 모듈로 N 계수기에서 생성된 클럭으로 자체 PN 코드를 발생시키는 구성으로 되어 있는 것이다.The module modifies the modulo N counter based on the point of time with the highest correlation value and generates its own PN code with the clock generated by the modulo N counter.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 DLL 방식에서의 다경로 페이딩 채널로 인한 S 커브에 미치는 영향을 나타낸 도면.1 is a diagram showing the effect on the S curve due to the multipath fading channel in the DLL scheme.
제2도는 본 발명의 병렬 상관기를 이용한 새로운 PN 코드 트랙킹장치의 블록 구성도.2 is a block diagram of a new PN code tracking device using the parallel correlator of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10a-10n : 다수개의 쉬프트 레지스터 20a-20n : 다수개의 곱셈기10a-10n: Multiple Shift Registers 20a-20n: Multiple Multipliers
30a-30n : 다수개의 적분기 40 : 선택부30a-30n: Multiple integrator 40: Selection part
50 : 모듈로(Modulo) 계수기 60 : PN 코드 생성기50: Modulo counter 60: PN code generator
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950050514A KR0155522B1 (en) | 1995-12-15 | 1995-12-15 | Spread spectrum pseudo noise code tracking device using parallel correllator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950050514A KR0155522B1 (en) | 1995-12-15 | 1995-12-15 | Spread spectrum pseudo noise code tracking device using parallel correllator |
Publications (2)
Publication Number | Publication Date |
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KR970056175A true KR970056175A (en) | 1997-07-31 |
KR0155522B1 KR0155522B1 (en) | 1998-11-16 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019950050514A KR0155522B1 (en) | 1995-12-15 | 1995-12-15 | Spread spectrum pseudo noise code tracking device using parallel correllator |
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KR (1) | KR0155522B1 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100532328B1 (en) * | 1998-08-29 | 2006-03-23 | 삼성전자주식회사 | P. Sequence Identifier of Code Division Multiple Access Communication System |
KR101961912B1 (en) | 2017-08-30 | 2019-03-28 | 한화시스템 주식회사 | Method for correlating signal |
KR20190032333A (en) | 2019-03-19 | 2019-03-27 | 한화시스템 주식회사 | Method for correlating signal |
KR20190033053A (en) | 2019-03-19 | 2019-03-28 | 한화시스템 주식회사 | Method for correlating signal |
CN110113074B (en) * | 2019-05-17 | 2021-02-26 | 中国电子科技集团公司第五十四研究所 | High-speed pseudo code parallel capturing and tracking method based on FPGA |
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1995
- 1995-12-15 KR KR1019950050514A patent/KR0155522B1/en not_active IP Right Cessation
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KR0155522B1 (en) | 1998-11-16 |
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