KR970055533A

KR970055533A - Output buffer

Info

Publication number: KR970055533A
Application number: KR1019950070197A
Authority: KR
Inventors: 천봉재
Original assignee: 문정환; Lg 반도체주식회사
Priority date: 1995-12-31
Filing date: 1995-12-31
Publication date: 1997-07-31

Abstract

본 발명은 출력 버퍼에 관한 것으로, 종래에는 풀업 소자와 풀다운소자의 턴은, 턴오프상태에 따라 출력단의 레벨이 변화하므로 하이에서 로우로의 데이타 천이 또는 로우에서 하이로의 데이타 천이상태에 따른 전류의 시간 변화율이 커서 잡음이 크게 발생하였고 또한, 풀업, 풀다운 소자에 따른 속도 지연이 발생하는 문제점이 있다. 이러한 종래의 문제점을 개선하기 위하여 본 발명은 고전압 입력되는 경우 출력단에 접속된 각각 2개인 풀업, 풀다운 소자를 각기 소정 시간 간격으로 동작시키므로써 시간 변화율에 인해 발생하는 잡음을 감소시킬 수 있고 또한 저전압이 입력되는 경우 출력단에 접속된 풀업, 풀다운 소자를 동시에 동작시키므로써 속도를 개선시킬 수 있도록 창안한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer. In the related art, since the level of the output stage changes according to the turn-off state, the turn-up and pull-down elements change the current according to the data transition from high to low or the data transition from low to high. Due to the large rate of change of time, noise is greatly generated, and there is a problem that a speed delay occurs due to pull-up and pull-down devices. In order to solve this problem, the present invention operates two pull-up and pull-down devices each connected to an output terminal at a predetermined time interval when a high voltage is input, thereby reducing noise caused by a rate of change of time, and In case of input, it is designed to improve speed by simultaneously operating pull-up and pull-down devices connected to the output terminal.

Description

Output buffer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 출력버퍼의 회로도.2 is a circuit diagram of an output buffer of the present invention.

Claims

A signal input unit 210 for inputting the input signal DIN according to the output enable signal OE and a delay unit for forming a current path with respect to the output signal of the signal input unit 210 according to the control signal CNTL ( And an output buffer 230 for precharging the output terminal OUTPUT according to the output signal of the delay unit 220 and the output signal of the signal input unit 210.

The delay unit 220 applies the output of the inverter IN2 of the signal input unit 210 to the transmission gate SW1 through the inverter IN7 and outputs the output of the inverter IN7 to the inverter IN8. (IN9) is sequentially applied to the transfer gate (SW2) and the output of the inverter IN4 of the signal input unit 210 is applied to the transfer gate (SW3) through the inverter IN10 and the output of the inverter (IN10) Inverters IN11 and IN12 are sequentially applied to the transfer gate SW4, and a control signal CNTL is applied to the non-inverting terminals of the transfer gates SW1 and SW3 and the inverting terminals of the transfer gates SW2 and SW4. And an inverter IN6 to which the control signal CNTL is applied is applied to the inverting terminal of the transfer gate SW1 and SW3 and the non-inverting terminal of the transfer gate SW2 and SW4 and to the transfer gate SW1. The output terminal of SW2 is applied to the gate of the PMOS transistor PM12 of the signal output unit 230, and the output terminal of the transfer gates SW3 and SW4 is applied to the gate of the PMOS transistor PM12. Gate is applied to the output buffer, characterized in that configured on the output ryeobu 230, NMOS transistor (NM12) for.

The signal output unit 230 applies two output signals of the signal input unit 210 to the PMOS transistor PM11 and the NMOS transistor NM11, respectively, and outputs two output signals of the delay unit 22. Is applied to the PMOS transistor PM12 and the NMOS transistor NM12, respectively, and the drains of the PMOS transistor PM11 (PM12) and the NMOS transistor NM11 (NM12) are connected in common, and the connection point thereof is the output terminal OUTPUT. Output buffer, characterized in that configured to be).

※ Note: The disclosure is based on the initial application.