KR970055363A - Data Clock Signal Generation Circuit Eliminating Noise - Google Patents

Data Clock Signal Generation Circuit Eliminating Noise Download PDF

Info

Publication number
KR970055363A
KR970055363A KR1019950050066A KR19950050066A KR970055363A KR 970055363 A KR970055363 A KR 970055363A KR 1019950050066 A KR1019950050066 A KR 1019950050066A KR 19950050066 A KR19950050066 A KR 19950050066A KR 970055363 A KR970055363 A KR 970055363A
Authority
KR
South Korea
Prior art keywords
noise
signal
receives
data clock
clock signal
Prior art date
Application number
KR1019950050066A
Other languages
Korean (ko)
Other versions
KR0182013B1 (en
Inventor
문승환
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950050066A priority Critical patent/KR0182013B1/en
Publication of KR970055363A publication Critical patent/KR970055363A/en
Application granted granted Critical
Publication of KR0182013B1 publication Critical patent/KR0182013B1/en

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0828—Several active elements per pixel in active matrix panels forming a digital to analog [D/A] conversion circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

이 발명은 박막트랜지스터(TFT;Thin Film Transistor) 액정표시장치(LCD :Liquid Crystal Display) 모듈(Module)에 사용되는 노이즈를 제거한 데이터 클록(DCLK;Data Clock) 신호 발생회로에 관한 것으로서, 입력되는 데이터 클록 신호(DCLKi(t))에서 저주파 성분의 노이즈를 제거하여 출력하는 저주파 노이즈 제거부(31)와; 상기한 저주파 노이즈 제거부(31)에서 출력된 신호(DCLKi(t))를 입력받아, 이 신호(DCLKi(t))를 고주파 성분의 노이즈를 제거할 수 있는 신호로 레벨 시프트하여 출력하는 레벨 시프트부(32)와; 상기한 레벨 시프트부(32)에서 출력된 신호(DCLK2(t))를 입력받아, 고주파 성분의 노이즈를 제거하고 반전하여 출력하는 슈미트 트리거 인버터(33)와; 상기한 슈미트 트리거 인버터(33)에서 출력되는 신호 (DCLK3(t))를 입력받아, 신호의 위상을 원래대로 하기 위해 반전하여, 안정된 데이터 클록 신호(DCLK4(t))를 출력하는 인버터(34)를 포함하여 이루어져서, 입력되는 데이터 클록 신호에서 저주파 및 고주파 노이즈 성분을 동시에 제거하여, 다양한 사용자 시스템에서의 부정합으로 인한 노이즈 발생 및 이로 인한 이상표시를 방지하고, 생산성도 높이는 효과를 가진, 노이즈를 제거한 데이터 클록 신호 발생회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a data clock (DCLK) signal generating circuit that removes noise used in a thin film transistor (TFT) liquid crystal display (LCD) module. A low frequency noise removing unit 31 which removes and outputs noise of low frequency components from the clock signal DCLKi (t); A level shift for receiving the signal DCLKi (t) output from the low frequency noise removing unit 31 and level shifting the signal DCLKi (t) to a signal capable of removing noise of a high frequency component. Section 32; A Schmitt trigger inverter 33 which receives the signal DCLK2 (t) output from the level shift unit 32, removes and inverts noise of high frequency components and outputs the inverted noise; Inverter 34 which receives the signal DCLK3 (t) output from the Schmitt-trigger inverter 33, inverts the signal to be in phase, and outputs a stable data clock signal DCLK4 (t). By removing the low-frequency and high-frequency noise components from the input data clock signal at the same time, to prevent the occurrence of noise due to mismatch in various user systems and resulting abnormal display, and to remove the noise, which has the effect of increasing the productivity A data clock signal generation circuit is provided.

Description

노이즈를 제거한 데이터 클록 신호 발생회로Data Clock Signal Generation Circuit Eliminating Noise

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 일반적인 박막트랜지스터 액정표시장치의 모듈을 나타낸 블록도이다.1 is a block diagram illustrating a module of a general thin film transistor liquid crystal display.

제2도는 종래에 사용한 데이터 클록 신호 발생신호를 나타낸 도면이다.2 is a diagram showing a data clock signal generation signal conventionally used.

Claims (6)

입력되는 데이터 클록 신호에서 저주파 성분의 노이즈를 제거하여 출력하는 저주파 노이즈 제거부와; 상기한 저주파 노이즈 제거부에서 출력된 신호를 입력받아, 이 신호를 고주파 성분의 노이즈를 제거할 수 있는 신호로 레벨 시프트하여 출력하는 레벨 시프트부와; 상기한 레벨 시프트부에서 출력된 신호를 입력받아, 고주파 성분의 노이즈를 제거하고 반전하여 출력하는 슈미트 트리거 인버터와; 상기한 슈미트 트리거 인버터에서 출력된 신호를 입력받아, 신호의 위상을 원래대로 하기 위해 반전하여, 안정된 데이터 클록 신호를 출력하는 인버터를 포함하여 이루어지는 것을 특징으로 하는 노이즈를 제거한 데이터 클록 신호 발생회로.A low frequency noise removing unit for removing noise of low frequency components from the input data clock signal and outputting the noise; A level shift unit which receives the signal output from the low frequency noise removing unit, and level shifts the signal into a signal capable of removing noise of a high frequency component; A Schmitt trigger inverter that receives the signal output from the level shift unit, removes and inverts noise of a high frequency component; And an inverter which receives the signal output from the Schmitt-trigger inverter, inverts the signal to be in phase, and outputs a stable data clock signal. 입력되는 데이터 클록 신호에서 저주파 성분의 노이즈를 제거하여 출력하는 저주파 노이즈 제거부와; 상기한 저주파 노이즈 제거부에서 출력된 신호를 입력받아, 큰 고주파 성분을 제거하여 출력하는 저역통과필터와; 상기한 저역통과필터에서 출력된 신호를 입력받아, 이 신호를 고주파 성분의 노이즈를 제거할 수 있는신호로 레벨 시프트하여 출력하는 레벨 시프트부와; 상기한 레벨 시프트부에서 출력된 신호를 입력받아, 고주파 성분의 노이즈를 제거하고 반전하여 출력하는 슈미트 트리거 인버터와; 상기한 슈미트 트리거 인버터에서 출력된 신호를 입력받아, 신호의 위상을 원래대로 하기 위해 반전하여, 안정된 데이터 클록 신호를 출력하는 인버터를 포함하여 이루어지는 것을 특징으로 하는 노이즈를 제거한 데이터 클록 신호 발생회로.A low frequency noise removing unit for removing noise of low frequency components from the input data clock signal and outputting the noise; A low pass filter which receives the signal output from the low frequency noise removing unit and removes and outputs a large high frequency component; A level shift unit which receives a signal output from the low pass filter and level shifts the signal into a signal capable of removing noise of a high frequency component; A Schmitt trigger inverter that receives the signal output from the level shift unit, removes and inverts noise of a high frequency component; And an inverter which receives the signal output from the Schmitt-trigger inverter, inverts the signal to be in phase, and outputs a stable data clock signal. 입력되는 데이터 클록 신호에서 저주파 성분의 노이즈를 제거하여 출력하는 저주파 노이즈 제거부와; 상기한 저주파 노이즈 제거부에서 출력된 신호를 입력받아, 이 신호를 고주파 성분의 노이즈를 제거할 수 있는 신호로 레벨 시프트하여 출력하는 레벨 시프트부와; 상기한 레벨 시프트부에서 출력된 신호를 입력받아, 큰 고주파 성분을 제거하여 출력하는 저역통과필터와; 상기 저역통과필터에서 출력된 신호를 입력받아, 고주파 성분의 노이즈를 제거하고 반전하여 출력하는 슈미트 트리거 인버터와; 상기한 슈미트 트리거 인버터에서 출력된 신호를 입력받아, 신호의 위상을 원래대로 하기 위해 반전하여, 안정된 데이터 클록 신호를 출력하는 인버터를 포함하여 이루어지는 것을 특징으로 하는 노이즈를 제거한 데이터 클록 신호 발생회로.A low frequency noise removing unit for removing noise of low frequency components from the input data clock signal and outputting the noise; A level shift unit which receives the signal output from the low frequency noise removing unit, and level shifts the signal into a signal capable of removing noise of a high frequency component; A low pass filter which receives the signal output from the level shift unit and removes and outputs a large high frequency component; A Schmitt trigger inverter that receives the signal output from the low pass filter, removes, inverts and outputs noise of a high frequency component; And an inverter which receives the signal output from the Schmitt-trigger inverter, inverts the signal to be in phase, and outputs a stable data clock signal. 제1항 내지 제3항에 있어서, 상기한 저주파 노이즈 제거부는, 정전용량의 한쪽단으로 상기한 입력 데이타 클록 신호(DCLKi(t))를 입력받고, 다른 한쪽단은 제1노드(N1)에 연결된 저주파 노이즈 성분 제거용 정합 커패시터(C1)와; 한쪽단이 제1노드(N1)에 연결되고, 다른 한쪽단이 그라운드에 연결되어, 기준 전위를 그라운드로 묶는 저항(R1)으로 이루어지는 것을 특징으로 하는 노이즈를 제거한 데이터 클록 신호 발생회로.The low frequency noise canceling unit according to claim 1, wherein the low frequency noise removing unit receives the input data clock signal DCLKi (t) at one end of the capacitance, and the other end thereof is input to the first node N1. A matching capacitor C1 for removing low frequency noise components; A noise canceling data clock signal generation circuit comprising one end connected to a first node (N1), the other end connected to ground, and a resistor (R1) for binding a reference potential to ground. 제1항 내지 제3항에 있어서, 상기한 레벨 시프트부는, 애노드로 일정 전압(Va)을 인가받고, 캐소드가 제2노드(N2)에 연결된 다이오드(D1)와; 한쪽단이 각 전단의 신호를 입력받고, 다른 한쪽단이 제2노드(N2)에 연결된 정합 커패시터 (C2)로 이루어지는 것을 특징으로 하는 노이즈를 제거한 데이터 클록 신호 발생회로.The method of claim 1, wherein the level shift unit comprises: a diode (D1) receiving a constant voltage (Va) as an anode and having a cathode connected to the second node (N2); A noise canceling data clock signal generating circuit, characterized in that one end receives a signal from each front end and the other end comprises a matching capacitor (C2) connected to a second node (N2). 제5항에 있어서, 상기한 일정 전압(Va)은 다음 식을 만족하는 것을 특징으로 하는 노이즈를 제거한 데이터 클록 신호 발생회로.6. The data clock signal generation circuit of claim 5, wherein the constant voltage Va satisfies the following equation. 0V 〈 Va 〈 Vs - Vd0V 〈Va 〈Vs-Vd 단, Vs는 슈미트 트리거링 전압, Vd는 다이오드(D1)에 의해 강하된 전압임.Where Vs is the Schmitt triggering voltage and Vd is the voltage dropped by the diode D1. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950050066A 1995-12-14 1995-12-14 Data Clock Signal Generation Circuit Eliminating Noise KR0182013B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950050066A KR0182013B1 (en) 1995-12-14 1995-12-14 Data Clock Signal Generation Circuit Eliminating Noise

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950050066A KR0182013B1 (en) 1995-12-14 1995-12-14 Data Clock Signal Generation Circuit Eliminating Noise

Publications (2)

Publication Number Publication Date
KR970055363A true KR970055363A (en) 1997-07-31
KR0182013B1 KR0182013B1 (en) 1999-04-15

Family

ID=19440182

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950050066A KR0182013B1 (en) 1995-12-14 1995-12-14 Data Clock Signal Generation Circuit Eliminating Noise

Country Status (1)

Country Link
KR (1) KR0182013B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100528021B1 (en) * 1999-03-20 2005-11-15 삼성전자주식회사 Source Signal Out Control Circuit Of a Source Drive IC Of an LCD

Also Published As

Publication number Publication date
KR0182013B1 (en) 1999-04-15

Similar Documents

Publication Publication Date Title
KR960036312A (en) Shift register
KR960035419A (en) Shift register
EP1014332A3 (en) Control device for a liquid crystal display apparatus
KR960035403A (en) Driving device of thin film transistor liquid crystal display
KR970071989A (en) Frequency multiplication circuit
KR910008964A (en) Frequency division circuits where the division ratio can be changed
KR970055363A (en) Data Clock Signal Generation Circuit Eliminating Noise
JPS6036137B2 (en) Frequency divider circuit
KR920001314A (en) Wide operating range automatic device for changing the horizontal deflection frequency of multi-sync monitor
KR960030069A (en) Apparatus and method for effective display center display of liquid crystal display device
KR0176173B1 (en) Frequency drain circuit and oscillator using same
US10649249B2 (en) Liquid crystal driving apparatus and liquid crystal driving method
KR940019073A (en) Floating detection circuit
KR100314962B1 (en) Circuit For Switching Synchronous Signal in Display Apparatus and Method thereof
KR950016272A (en) Clock synchronization circuit
KR960025760A (en) Charge pump circuit
KR950027439A (en) Wide Vision Driving Circuit by Sampling Clock Modulation
SU807474A1 (en) Synchronyzable self-excited oscillator
KR910020526A (en) Vision automatic adjustment circuit
JP4962759B2 (en) Pulse signal generator and clock signal generator
KR970008878A (en) Clock switching circuit
KR970029299A (en) Noise elimination circuit of liquid crystal display (LCD)
KR930022716A (en) Waveform generation circuit
KR930014509A (en) High resolution video signal processing device using low frequency oscillator
KR930003520A (en) Frequency modulation circuit

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19951214

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19951214

Comment text: Request for Examination of Application

PG1501 Laying open of application
E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 19980615

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 19981123

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 19981210

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 19981210

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20011107

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20021108

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20031107

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20041105

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 20051109

Start annual number: 8

End annual number: 8

PR1001 Payment of annual fee

Payment date: 20061128

Start annual number: 9

End annual number: 9

PR1001 Payment of annual fee

Payment date: 20071127

Start annual number: 10

End annual number: 10

PR1001 Payment of annual fee

Payment date: 20081128

Start annual number: 11

End annual number: 11

PR1001 Payment of annual fee

Payment date: 20091113

Start annual number: 12

End annual number: 12

PR1001 Payment of annual fee

Payment date: 20101112

Start annual number: 13

End annual number: 13

FPAY Annual fee payment

Payment date: 20111115

Year of fee payment: 14

PR1001 Payment of annual fee

Payment date: 20111115

Start annual number: 14

End annual number: 14

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

Termination category: Default of registration fee

Termination date: 20131109