KR970054474A

KR970054474A - High voltage semiconductor device and manufacturing method

Info

Publication number: KR970054474A
Application number: KR1019950066072A
Authority: KR
Inventors: 박상준
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1995-12-29
Filing date: 1995-12-29
Publication date: 1997-07-31

Abstract

본 발명은 고전압 반도체 소자 및 그 제조방법에 관한 것으로서, P형 기판상에 N웰을 형성하고, 상기 N웰의 중간에 P+영역을 형성하며 PNPN로 구성되는 접합을 형성하고, 중간의 접합에는 전위를 결정하지 않도록 하는 구조로 고전압 반도체 소자를 형성하였으므로, N웰 전압이 0이하인 구간에서 N웰과 반도체 기판간의 접합 리키지가 거의 없고, N웰과 반도체 기판 사이의 불순물 영역에서는 바이어스에 따른 전위가 유동적으로 바뀌어 N웰쪽이 디프리션 확장이 거의 일어나지 않아 활용 가능한 N웰의 깊이가 증가되며, 반도체기판쪽의 디프리션도 작아 소자의 집적도를 향상시킬 수 있고, 수직 방향의 전류가 매우 작어 래치업과 브레이크 다운 및 펀치쓰로 특성이 향상된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage semiconductor device and a method of manufacturing the same, wherein an N well is formed on a P-type substrate, a P + region is formed in the middle of the N well, and a junction composed of PNPN is formed. Since the high-voltage semiconductor device is formed so as not to determine, there is almost no junction risk between the N well and the semiconductor substrate in the section where the N well voltage is 0 or less, and the potential due to the bias flows in the impurity region between the N well and the semiconductor substrate. As the N well side hardly despreads expansion, the depth of the N well that can be used is increased, and the depth of the semiconductor substrate is small, so that the integration of the device can be improved, and the vertical current is very small, so the latch-up and Breakdown and punching improve the characteristics.

Description

High voltage semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1F도는 본 발명에 따른 고전압 반도체 소자의 제조 공정도.1A to 1F are manufacturing process diagrams of a high voltage semiconductor device according to the present invention.

Claims

Wells of the second conductivity type formed on the semiconductor substrate of the first conductivity type, First impurity regions formed in the middle of the wells of the second conductivity type, and Moss formed on the semiconductor substrate. A high voltage semiconductor device having a field effect transistor.

2. The high voltage semiconductor device of claim 1, wherein a first conductive impurity region and a lower first conductive well positioned between the semiconductor substrate and the upper first conductive portion are electrically floating.

Forming a second conductive well on the first conductive semiconductor substrate, forming a first conductive impurity region in the middle of the second conductive well, and being formed on the semiconductor substrate A method of manufacturing a high voltage semiconductor device comprising the step of forming a MOS field effect transistor.

※ Note: The disclosure is based on the initial application.