KR970054177A - High Efficiency High Speed Synchronous Mask Rom - Google Patents
High Efficiency High Speed Synchronous Mask Rom Download PDFInfo
- Publication number
- KR970054177A KR970054177A KR1019950054619A KR19950054619A KR970054177A KR 970054177 A KR970054177 A KR 970054177A KR 1019950054619 A KR1019950054619 A KR 1019950054619A KR 19950054619 A KR19950054619 A KR 19950054619A KR 970054177 A KR970054177 A KR 970054177A
- Authority
- KR
- South Korea
- Prior art keywords
- clock
- mask rom
- high speed
- synchronous
- speed
- Prior art date
Links
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/06—Address interface arrangements, e.g. address buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Read Only Memory (AREA)
Abstract
본 발명은 고효율 고속 동기형 마스크 롬에 관한 것이다.The present invention relates to a high efficiency high speed synchronous mask ROM.
종래 동기형 마스크 롬은 그 응용분야인 전자수첩이나 프린터등의 사무 자동화기기 그리고 빠른 속도를 요구 하는 게임기등에 사용할 경우 많은 전력을 소모할 뿐만 아니라 외부의 동기 클럭이 변했을 때 이를 수용할 없어 항상 외부의 클럭 속도를 알고 다음에 동기형 마스클 롬을 설계해아 하는 번거로움 및 판매시기를 맞추기 어려운 문제점이 있었다.Conventional synchronous mask ROM not only consumes a lot of power when used in application fields such as electronic notebooks, printers, office automation devices, and game machines that require high speed, but also cannot accommodate when the external synchronous clock changes. Knowing the clock speed and then having to design a synchronous masque next time has been a difficult and time-to-market problem.
따라서 본 발명은 상기한 종래기술의 문제점을 개선코자 하여 안출되니 것으로서, 클럭신호와 래치회로를 추가하고 마스크 롬의 각 블럭을 세부적으로 나누어 기존의 동기형 마스크 롬과 같이 슈퍼 파이프(Super Pipeline) 방식의개념을 도입하고 외부 클럭속도를 빠른 속도로 적응하는 회로를 추가하고 또한 저전압에서 동작할 수 있도록 전원레벨 변환기(Voltage Down Converter)를 사용함으로서, 고효율 및 고속화 하도록 하는 것이다.Therefore, the present invention is devised to improve the above-described problems of the prior art, and adds a clock signal and a latch circuit, and divides each block of the mask ROM in detail, such as a super pipeline scheme like a conventional synchronous mask ROM. Introducing the concept, adding a circuit that adapts the external clock speed at a high speed, and using a voltage down converter to operate at a low voltage, thereby increasing efficiency and speed.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 의한 고효율 고속동기형 마스크 롬의 블록 구성도.2 is a block diagram of a high-efficiency high-speed synchronous mask ROM according to the present invention.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950054619A KR100228422B1 (en) | 1995-12-22 | 1995-12-22 | High-efficient high-speed synchronous mask rom |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950054619A KR100228422B1 (en) | 1995-12-22 | 1995-12-22 | High-efficient high-speed synchronous mask rom |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970054177A true KR970054177A (en) | 1997-07-31 |
KR100228422B1 KR100228422B1 (en) | 1999-11-01 |
Family
ID=19443191
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950054619A KR100228422B1 (en) | 1995-12-22 | 1995-12-22 | High-efficient high-speed synchronous mask rom |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100228422B1 (en) |
-
1995
- 1995-12-22 KR KR1019950054619A patent/KR100228422B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100228422B1 (en) | 1999-11-01 |
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Legal Events
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A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20060720 Year of fee payment: 8 |
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LAPS | Lapse due to unpaid annual fee |