KR970053585A - Method for forming contact hole buried plug in semiconductor device - Google Patents
Method for forming contact hole buried plug in semiconductor device Download PDFInfo
- Publication number
- KR970053585A KR970053585A KR1019950069608A KR19950069608A KR970053585A KR 970053585 A KR970053585 A KR 970053585A KR 1019950069608 A KR1019950069608 A KR 1019950069608A KR 19950069608 A KR19950069608 A KR 19950069608A KR 970053585 A KR970053585 A KR 970053585A
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- KR
- South Korea
- Prior art keywords
- etching
- contact hole
- plug
- film
- until
- Prior art date
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 콘택홀이나 비아홀에 금속 플러그 형성시 단차(topology) 부위에 잔류하는 금속층을 효과적으로 제거하는 동시에 플러그의 침식에 대비할 수 있는 반도체 소자의 콘택홀 매립 플러그 형성방법을 제공하기 위한 것이다.An object of the present invention is to provide a method of forming a contact hole buried plug in a semiconductor device capable of effectively removing a metal layer remaining in a topology portion when forming a metal plug in a contact hole or a via hole and preparing for erosion of the plug.
이와 같은 목적을 달성하기 위한 본 발명의 콘택홀 매립 플러그 형성방법은 반도체 기판 상부의 산화막의 소정 부위에 형성된 콘택홀의 전면에 콘택홀을 충분히 매립할 정도의 소정 두께로 금속막을 증착하는 단계; 증착된 금속막을 산화막이 드러날 때까지 전면 식각하는 단계; 글로벌 단차 지역의 잔류 금속막이 제거될 때까지 건식식각하는 단계; 상기 단계에서 잔류물의 식각과 함께 식각된 플러그의 표면이 노출될 때까지 산화막을 전면 식각하는 단계; 전면에 금속배선막을 증착하고 사진식각 방법을 이용하여 금속배선 패턴을 형성하는 단계를 포함하는 것을 특징으로 한다.A method of forming a contact hole filling plug according to an embodiment of the present invention includes: depositing a metal film having a predetermined thickness sufficient to fill a contact hole in an entire surface of a contact hole formed at a predetermined portion of an oxide film on a semiconductor substrate; Etching the deposited metal film until the oxide film is exposed; Dry etching until the residual metal film of the global step area is removed; Etching the entire oxide film until the surface of the etched plug is exposed together with etching the residue in the step; And depositing a metal wiring layer on the entire surface and forming a metal wiring pattern using a photolithography method.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2도는 본 발명의 실시예에 따른 반도체 소자의 콘택홀 매립 플러그 형성방법을 설명하기 위한 공정 흐름도이다.2 is a flowchart illustrating a method of forming a contact hole buried plug in a semiconductor device according to an exemplary embodiment of the present invention.
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950069608A KR970053585A (en) | 1995-12-30 | 1995-12-30 | Method for forming contact hole buried plug in semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950069608A KR970053585A (en) | 1995-12-30 | 1995-12-30 | Method for forming contact hole buried plug in semiconductor device |
Publications (1)
Publication Number | Publication Date |
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KR970053585A true KR970053585A (en) | 1997-07-31 |
Family
ID=66638730
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950069608A KR970053585A (en) | 1995-12-30 | 1995-12-30 | Method for forming contact hole buried plug in semiconductor device |
Country Status (1)
Country | Link |
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KR (1) | KR970053585A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19990057826A (en) * | 1997-12-30 | 1999-07-15 | 김영환 | Metal wiring formation method of semiconductor device |
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1995
- 1995-12-30 KR KR1019950069608A patent/KR970053585A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19990057826A (en) * | 1997-12-30 | 1999-07-15 | 김영환 | Metal wiring formation method of semiconductor device |
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