KR970052220A - Polysilicon layer formation method of semiconductor device - Google Patents

Polysilicon layer formation method of semiconductor device Download PDF

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Publication number
KR970052220A
KR970052220A KR1019950048749A KR19950048749A KR970052220A KR 970052220 A KR970052220 A KR 970052220A KR 1019950048749 A KR1019950048749 A KR 1019950048749A KR 19950048749 A KR19950048749 A KR 19950048749A KR 970052220 A KR970052220 A KR 970052220A
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KR
South Korea
Prior art keywords
polysilicon layer
gas
amorphous
semiconductor device
rate
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KR1019950048749A
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Korean (ko)
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KR0184942B1 (en
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오훈정
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김주용
현대전자산업 주식회사
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Priority to KR1019950048749A priority Critical patent/KR0184942B1/en
Publication of KR970052220A publication Critical patent/KR970052220A/en
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Publication of KR0184942B1 publication Critical patent/KR0184942B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material

Abstract

본 발명은 반도체 소자의 폴리실리콘층 형성방법을 제공하는 것으로 실리콘기판상에 비정질 인 도프 폴리실리콘층을 형성하고, 상기 비정질 인 도프 폴리실리콘층상의 표면에 N2및 O2의 혼합가스를 이용하여 표면 처리를 한 후 열처리공정에 의해 상기 비정질 인 도프 폴리실리콘층을 결정화시키므로써 표면의 거칠기를 감소시켜 소자의 수율을 향상시킬 수 있는 효과가 있다.The present invention provides a method for forming a polysilicon layer of a semiconductor device, by forming an amorphous dope polysilicon layer on a silicon substrate, using a mixed gas of N 2 and O 2 on the surface of the amorphous dope polysilicon layer After the surface treatment, the amorphous dope polysilicon layer is crystallized by a heat treatment process, thereby reducing the surface roughness, thereby improving the yield of the device.

Description

반도체 소자의 폴리실리콘층 형성방법Polysilicon layer formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1a도 내지 제1c도는 본 발명에 따른 반도체 소자의 폴리실리콘층 형성방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method of forming a polysilicon layer of a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘기판1: silicon substrate

2A : 비정질 인(P) 도프 폴리실리콘층2A: Amorphous Phosphorus (P) Doped Polysilicon Layer

2B : 표면 처리된 비정질 인(P) 도프 폴리실리콘층2B: A surface-treated amorphous phosphor (P) dope polysilicon layer

2C : 결정화된 폴리실리콘층2C: Crystallized Polysilicon Layer

Claims (11)

반도체 소자의 폴리실리콘층 형성방법에 있어서, 실리콘기판상에 비정질 인 도프 폴리실리콘층을 형성하는 제 1단계와, 상기 제 1단계로부터 상기 비정질 인 도프 폴리실리콘층상의 표면에 실리콘 원자의 이동을 차단하기 위하여 소정의 가스를 이용하여 표면처리를 행하는 제 2단계와, 상기 제 2단계로부터 표면 처리된 상기 비정질 인 도프 폴리실리콘층에 열처리공정을 실시하여 결정화된 폴리실리콘층을 형성하는 제 3단계로 이루어지는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 형성방법.A method for forming a polysilicon layer of a semiconductor device, the method comprising: forming an amorphous dope polysilicon layer on a silicon substrate; and blocking movement of silicon atoms on the surface of the amorphous dope polysilicon layer from the first step In order to form a crystallized polysilicon layer by performing a heat treatment process on the amorphous phosphor-doped polysilicon layer surface-treated from the second stage. A method for forming a polysilicon layer of a semiconductor device, characterized in that. 제 1항에 있어서, 제 1단계공정은 510 내지 530℃의 온도와, 0.9 내지 1.0Torr의 압력과 PH3및 SiH4가스의 조건으로 실시되는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 형성방법The method of claim 1, wherein the first step is performed under conditions of a temperature of 510 to 530 ° C., a pressure of 0.9 to 1.0 Torr, and a PH 3 and SiH 4 gas. 제 2항에 있어서, 상기 SiH4가스는 실리콘 소스가스로 사용하고, PH3가스는 도펀트가스로 사용하는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 형성방법.The method of claim 2, wherein the SiH 4 gas is used as a silicon source gas, and the PH 3 gas is used as a dopant gas. 제 2항에 있어서, 상기 PH3및 SiH4의 가스흐름비율은 0.04 내지 0.06%로 하고, 전체반응가스 플로우량은 1000 내지 1200SCCM으로 하는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 형성방법.3. The method of claim 2, wherein the gas flow rate of the PH 3 and SiH 4 is 0.04 to 0.06%, and the total reaction gas flow rate is 1000 to 1200SCCM. 제 1항에 있어서, 상기 표면 처리는 O2및 N2의 혼합가스를 사용하는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 형성방법.The method of claim 1, wherein the surface treatment uses a mixed gas of O 2 and N 2 . 제 5항에 있어서, 상기 혼합가스는 순수한 N2가스에 8 내지 12%의 O2가스를 희석시키는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 형성방법The method of claim 5, wherein the mixed gas dilutes 8 to 12% O 2 gas in pure N 2 gas. 제 1항에 있어서, 상기 표면처리는 15 내지 25SLPM의 혼합가스 플로우량으로 20 내지 40분간 정화하는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 형성방법.The method of claim 1, wherein the surface treatment is purged for 20 to 40 minutes with a mixed gas flow amount of 15 to 25 SLPM. 제 1항에 있어서, 상기 열처리공정은 5℃/min의 속도로 600 내지 650℃까지 증가하도록 가열하고, 상기 600 내지 650℃에서는 100 내지 140분 동안 가열한 후 5 내지 10℃/min의 속도로 400℃까지 하강하도록 냉각시키는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 형성방법.According to claim 1, wherein the heat treatment is heated to increase to 600 to 650 ℃ at a rate of 5 ℃ / min, at 600 to 650 ℃ after heating for 100 to 140 minutes at a rate of 5 to 10 ℃ / min A method for forming a polysilicon layer of a semiconductor device, characterized in that cooling to fall to 400 ℃. 제 1항에 있어서, 상기 열처리공정은 순수한 N2가스를 15 내지 25SLPM으로 공급하여 실시하는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 형성방법.The method of claim 1, wherein the heat treatment is performed by supplying pure N 2 gas at 15 to 25 SLPM. 제 1항에 있어서, 상기 제 2단계공정은 비정질 인 도프 폴리실리콘층상에서 실리콘 원자의 이동을 차단하기 위하여 상기 비정질 인 도프 폴리실리콘층상의 표면을 20 내지 30℃/min의 속도로 350 내지 400℃까지 냉각시키면서 N2가스를 사용하여 대기압 상태로 만든 후 8 : 2의 비율로 혼합한 N2: O2가스로 60 내지 90분동안 정화시켜 표면처리를 행하는 것을 특징으로 하는 반도체소자의 폴리실리콘층 형성방법.The method of claim 1, wherein the second step is performed in order to block the movement of silicon atoms on the amorphous dope polysilicon layer at a rate of 350 to 400 ° C. at a rate of 20 to 30 ° C./min. The polysilicon layer of the semiconductor device, characterized in that the surface treatment by performing a surface treatment by cooling to 60 ℃ N 2 : O 2 gas at a ratio of 8: 2 after making to atmospheric pressure using N 2 gas Formation method. 제 1항에 있어서, 상기 제 3단계공정은 비정질 인 도프 폴리실리콘층을 로딩시 600℃이하로 하고 5℃/min이하의 속도로 후속공정 온도까지 상승시키는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 형성방법.The polysilicon layer of claim 1, wherein the third step process comprises raising the amorphous dope polysilicon layer to 600 ° C. or less at a loading and to a subsequent process temperature at a rate of 5 ° C./min or less. Formation method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950048749A 1995-12-12 1995-12-12 Method of forming polysilicon layer of semiconductor device KR0184942B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100525436B1 (en) * 2001-05-25 2005-11-02 엘지.필립스 엘시디 주식회사 Process for crystallizing amorphous silicon and its application - fabricating method of TFT-LCD

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100525436B1 (en) * 2001-05-25 2005-11-02 엘지.필립스 엘시디 주식회사 Process for crystallizing amorphous silicon and its application - fabricating method of TFT-LCD

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