KR970051936A - Overlap arrangement between gate and source / drain to correct stitching - Google Patents

Overlap arrangement between gate and source / drain to correct stitching Download PDF

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Publication number
KR970051936A
KR970051936A KR1019950068231A KR19950068231A KR970051936A KR 970051936 A KR970051936 A KR 970051936A KR 1019950068231 A KR1019950068231 A KR 1019950068231A KR 19950068231 A KR19950068231 A KR 19950068231A KR 970051936 A KR970051936 A KR 970051936A
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KR
South Korea
Prior art keywords
electrode
drain
source
gate
stitch
Prior art date
Application number
KR1019950068231A
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Korean (ko)
Other versions
KR0169358B1 (en
Inventor
이제상
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950068231A priority Critical patent/KR0169358B1/en
Publication of KR970051936A publication Critical patent/KR970051936A/en
Application granted granted Critical
Publication of KR0169358B1 publication Critical patent/KR0169358B1/en

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Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching

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  • Liquid Crystal (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 드레인 전극에 별도의 스티치 보정 전극을 적용하여 인접 게이트선에 오버랩 시킴으로써, 스티치 오차 발생에 의한 기생 용량 값의 변화를 보정하여 블럭 결함을 방지하는 액정 표시 장치의 제조 방법에 관한 것이다. 게이트 전극과 소스 전극 사이에서 형성되는 기생 용량의 크기는 게이트 전극과 드레인 전극의 오버랩되는 면적이 결정하므로, 그 면적과 동일하면서, 폭이 동일하도록 스티치 오차 보정용 전극을 드레인 전극에 연결되게 형성하기 때문에, 게이트 전극과 드레인 전극의 오버랩되는 면적과 동일한 크기를 갖는 스티치 오차 보정용 전극을 형성하면, 스티치 오차 보정용 전극과 인접 게이트 배선과의 사이에서 오버랩되어 형성되는 면적이 같게 된다. 따라서 공정 중에 부정합이 발생하더라도 기생 용량의합이 일정하여 화상 정보의 변화를 막을 수 있다.The present invention relates to a method of manufacturing a liquid crystal display device that prevents block defects by applying a separate stitch correction electrode to a drain electrode and overlapping adjacent gate lines, thereby correcting a change in a parasitic capacitance value caused by a stitch error. Since the size of the parasitic capacitance formed between the gate electrode and the source electrode is determined by the overlapping area of the gate electrode and the drain electrode, the stitch error correction electrode is formed to be connected to the drain electrode so as to have the same width but the same width. When the stitch error correction electrode having the same size as the overlapping area of the gate electrode and the drain electrode is formed, the area formed by overlapping between the stitch error correction electrode and the adjacent gate wiring becomes the same. Therefore, even if a mismatch occurs in the process, the sum of parasitic capacitances is constant to prevent the change of image information.

Description

스티치 현상을 보정할 수 있는 게이트와 소스/드레인 간의 오버랩 배열Overlap arrangement between gate and source / drain to correct stitching

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 실시예에 따른 샷의 배열을 나타낸 평면도이고,3 is a plan view showing an arrangement of shots according to an embodiment of the present invention,

Claims (6)

게이트 위에 소스/드레인을 형성시, 서로 다른 형태의 패턴이 다수로 배열되어 있는 샷을 이용하여 소스/드레인을 형성하는 것을 포함하는 액정 표시 장치용 박막 트랜지스터의 제조 방법.A method of manufacturing a thin film transistor for a liquid crystal display device, the method including forming a source / drain using a shot in which a plurality of patterns of different shapes are arranged when forming a source / drain on a gate. 제1항에서, 상기 샷은 서로 다른 형태의 패턴이 불규칙한 형태로 배열되어 있는 액정 표시 장치용 박막 트랜지스터의 제조 방법.The method of claim 1, wherein the shots are arranged in an irregular shape with different patterns. 제1항 또는 제2항에서, 상기 샷의 서로 다른 패턴은 기준 패턴을 중심으로 소스/드레인이 소정의 크기로 쉬프트 되게 형성하는 액정 표시 장치용 박막 트랜지스터의 제조 방법.The method of claim 1, wherein the different patterns of the shot are formed such that the source / drain is shifted to a predetermined size with respect to the reference pattern. 제3항에서, 상기 소스/드레인이 소정의 크기로 쉬프트 되게 형성할 때, 쉬프트되는 소정의 크기는 0.25㎛의 간격으로 형성하는 액정 표시 장치용 박막 트랜지스터의 제조 방법.The method of claim 3, wherein when the source / drain is shifted to a predetermined size, the shifted predetermined size is formed at an interval of 0.25 μm. 제3항에서, 상기 샷의 서로 다른 패턴은 5종류의 패턴으로 형성하는 액정 표시 장치용 박막 트랜지스터의 제조 방법.The method of claim 3, wherein the different patterns of the shot are formed into five types of patterns. 제5항에서, 상기 5종류의 패턴은 기준치를 중심으로 -0.5㎛에서 +0.5㎛ 까지 허용치를 갖도록 형성하는 액정 표시 장치용 박막 트랜지스터의 제조 방법.The method of manufacturing a thin film transistor for a liquid crystal display device according to claim 5, wherein the five kinds of patterns are formed to have an allowable value from -0.5 μm to +0.5 μm around the reference value. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950068231A 1995-12-30 1995-12-30 Overlap align correcting stitch between gate and source/drain KR0169358B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950068231A KR0169358B1 (en) 1995-12-30 1995-12-30 Overlap align correcting stitch between gate and source/drain

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950068231A KR0169358B1 (en) 1995-12-30 1995-12-30 Overlap align correcting stitch between gate and source/drain

Publications (2)

Publication Number Publication Date
KR970051936A true KR970051936A (en) 1997-07-29
KR0169358B1 KR0169358B1 (en) 1999-02-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950068231A KR0169358B1 (en) 1995-12-30 1995-12-30 Overlap align correcting stitch between gate and source/drain

Country Status (1)

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KR (1) KR0169358B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990003280A (en) * 1997-06-25 1999-01-15 윤종용 Panel for liquid crystal display device which reduced flicker

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990003280A (en) * 1997-06-25 1999-01-15 윤종용 Panel for liquid crystal display device which reduced flicker

Also Published As

Publication number Publication date
KR0169358B1 (en) 1999-02-01

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