KR970051450A - Redundancy cell arrangement method of semiconductor memory device - Google Patents

Abstract

The present invention relates to a method of arranging redundancy cells in a semiconductor memory device, and more particularly, to a method of arranging redundancy cells for effectively arranging redundancy fuse boxes. The present invention relates to a method of arranging a redundancy cell of a semiconductor memory device including a plurality of memory cell arrays, wherein at least one redundancy word line for controlling a low redundancy cell is disposed in each of the memory cell arrays and adjacent to each other. The redundancy word lines are positioned at least one, the number of the redundancy word lines of the neighboring memory cell arrays are different from each other, and a redundancy fuse box is disposed adjacent to each of the redundancy word lines. It is also possible to apply the concept of the present invention to column redundancy. Therefore, the present invention increases the number of redundancy by half compared to the case where one spare word line SWL is positioned for each memory cell array, and also maintains the size of the fuse layer without increasing the fuse layer. have. This allows for increased redundancy without the burden of placement due to the increase in fuse boxes.

Description

Redundancy cell arrangement method of semiconductor memory device

As this is a public information case, the full text was not included.

3 is a diagram illustrating a method of arranging redundancy cells according to the first embodiment of the present invention.

4 is a diagram illustrating a method of arranging redundancy cells according to the second chamber of the present invention.

Claims (4)

A redundancy cell arrangement method of a semiconductor memory device comprising a plurality of memory cell arrays, wherein at least one redundancy word line controlling a low redundancy cell is disposed in each of the two memory cell arrays, and the redundancy of the memory cell arrays adjacent to each other is provided. A redundancy cell arrangement method for a semiconductor memory device, characterized in that the number of word lines has a different structure. A redundancy cell arrangement method of a semiconductor memory device including a plurality of memory cell arrays, wherein at least one redundancy word line controlling a low redundancy cell is disposed in each of the memory cell arrays, and the redundancy word of the memory cell arrays adjacent to each other is disposed. A redundancy cell arrangement method for a semiconductor memory device, characterized in that the number of lines is different and a redundancy fuse box is arranged adjacent to each redundancy word line. A redundancy cell arrangement method of a semiconductor memory device including a plurality of memory cell arrays, wherein at least one redundancy bit line constituting a column redundancy cell is positioned in each memory cell array, and the redundancy bits of the neighboring memory cell arrays are located. A redundancy cell arrangement method for a semiconductor memory device, characterized in that the number of lines has a different structure. A redundancy cell arrangement method of a semiconductor memory device including a plurality of memory cell arrays, wherein at least one redundancy bit line constituting a column redundancy cell is positioned in each memory cell array, and the redundancy bit lines of neighboring memory cell arrays are located. The redundancy cell arrangement method of a semiconductor memory device, characterized in that the number of different from each other, and the redundancy fuse box is disposed adjacent to each of the redundancy bit line. ※ Note: The disclosure is based on the initial application.