KR970051343A - Program and erase voltage application method and circuit of nonvolatile semiconductor memory device - Google Patents

Program and erase voltage application method and circuit of nonvolatile semiconductor memory device Download PDF

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Publication number
KR970051343A
KR970051343A KR1019950053528A KR19950053528A KR970051343A KR 970051343 A KR970051343 A KR 970051343A KR 1019950053528 A KR1019950053528 A KR 1019950053528A KR 19950053528 A KR19950053528 A KR 19950053528A KR 970051343 A KR970051343 A KR 970051343A
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KR
South Korea
Prior art keywords
voltage
program
erase
nonvolatile semiconductor
semiconductor memory
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Application number
KR1019950053528A
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Korean (ko)
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KR0172417B1 (en
Inventor
정태성
용명식
Original Assignee
김광호
삼성전자 주식회사
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Priority to KR1019950053528A priority Critical patent/KR0172417B1/en
Publication of KR970051343A publication Critical patent/KR970051343A/en
Application granted granted Critical
Publication of KR0172417B1 publication Critical patent/KR0172417B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

불휘발성 반도체 메모리장치의 프로그램 및 소거전압 인가방법 및 회로.Program and erase voltage application method and circuit of a nonvolatile semiconductor memory device.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

셀의 스트레스를 줄일 수 있는 불휘발성 반도체 메모리 장치의 프로그램 및 소거전압 인가방법 및 그에 따른 전압발생 회로를 제공함에 있다.The present invention provides a method of applying a program and an erase voltage to a nonvolatile semiconductor memory device which can reduce stress of a cell, and a voltage generation circuit according thereto.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

프로그램 동작과 프로그램 검증동작이 연속적으로 행해지는 불휘발성 반도체 메모리의 프로그램 전압 인가방법은, 프로그램 동작의 수행시 프로그램 횟수의 증가시마다 프로그램 전압을 소정 전압의 범위내에서 순차적으로 증가시켜 인가하되, 상기 프로그램 전압을 펄스형태로 발생시켜 상기 메모리의 워드라인에 제공하는 것을 특징으로 한다.In the method of applying a program voltage to a nonvolatile semiconductor memory in which a program operation and a program verifying operation are continuously performed, the program voltage is sequentially increased and applied within a range of a predetermined voltage every time the number of programs is increased during the program operation. The voltage is generated in the form of a pulse and provided to the word line of the memory.

4. 발명의 중요한 용도4. Important uses of the invention

콤퓨터등에 사용되는 영구 메모리.Permanent memory used for computers.

Description

불휘발성 반도체 메모리장치의 프로그램 및 소거전압 인가방법 및 회로Program and erase voltage application method and circuit of nonvolatile semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명에 따른 프로그램 및 소거전압을 발생하기 위한 고전압 발생회로의 블록도.5 is a block diagram of a high voltage generation circuit for generating program and erase voltages in accordance with the present invention.

Claims (3)

프로그램 동작과 프로그램 검증동작이 연속적으로 행해지는 불휘발성 반도체 메모리의 프로그램 전압 인가방법에 있어서, 프로그램 동작의 수행시 프로그램 횟수의 증가시마다 프로그램 전압을 소정 전압의 범위내에서 순차적으로 증가시켜 인가하되, 한주기의 프로그램 전압마다 다수의 펄스형태로 발생시켜 상기 메모리의 워드라인에 제공하는 것을 특징으로 하는 방법.In the method of applying a program voltage to a nonvolatile semiconductor memory in which a program operation and a program verify operation are performed continuously, the program voltage is sequentially increased within a predetermined voltage and applied every time the number of programs is increased during the program operation. Generating a plurality of pulses for each predetermined program voltage and providing the same to a word line of the memory. 불휘발성 반도체 메모리의 고전압 발생회로에 있어서, 고전압을 발생시키는 차아지 펌프, 상기 차아지 펌프로부터 발생된 전압의 레벨을 검출하고 프로그램 루프검출기의 출력에 의해 제어되는 레벨 검출기, 상기 레벨 검출기의 출력전압과 인가되는 기준전압을 비교하는 비교부, 상기 비교부의 출력 비교신호에 응답하여 상기 차아지 펌프의 동작을 제어하는 제어부, 및 상기 차아지 펌프로부터 발생된 전압을 미리 설정된 카운팅 주기에 맞추어 펄스형태로 출력시켜 이를 프로그램 또는 소거전압으로서 생성하는 출력전압 정형부를 가짐을 특징으로 하는 회로.A high voltage generation circuit of a nonvolatile semiconductor memory, comprising: a charge pump for generating a high voltage, a level detector for detecting a level of a voltage generated from the charge pump and controlled by an output of a program loop detector; an output voltage of the level detector And a comparison unit for comparing a reference voltage applied to the control unit, a control unit controlling the operation of the charge pump in response to an output comparison signal of the comparison unit, and a voltage generated from the charge pump in a pulse form in accordance with a preset counting period. And an output voltage shaping portion that outputs and generates it as a program or erase voltage. 소거 동작과 소거 검증동작이 연속적으로 행해지는 불휘발성 반도체 메모리의 소거 전압 인가방법에 있어서, 소거 동작의 수행시 소거 횟수의 증가시마다 소거전압을 소정 전압의 범위내에서 순차적으로 증가시켜 인가하되, 상기 소거전압을 펄스형태로 발생시켜 상기 메모리의 워드라인에 제공하는 것을 특징으로 하는 방법.An erase voltage application method of a nonvolatile semiconductor memory in which an erase operation and an erase verify operation are performed continuously, wherein the erase voltage is sequentially increased within a range of a predetermined voltage every time the erase count is increased during the erase operation. Generating an erase voltage in the form of a pulse and providing the erase voltage to a word line of the memory. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950053528A 1995-12-21 1995-12-21 Method and circuit for applying program and erase voltage in non-volatile semiconductor memory device KR0172417B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950053528A KR0172417B1 (en) 1995-12-21 1995-12-21 Method and circuit for applying program and erase voltage in non-volatile semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950053528A KR0172417B1 (en) 1995-12-21 1995-12-21 Method and circuit for applying program and erase voltage in non-volatile semiconductor memory device

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KR970051343A true KR970051343A (en) 1997-07-29
KR0172417B1 KR0172417B1 (en) 1999-03-30

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990072291A (en) * 1998-02-12 1999-09-27 피터 토마스 Electronically programmable read-only memory and method for programming and reading the memory

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101495789B1 (en) * 2008-11-17 2015-02-26 삼성전자주식회사 Memory device and programming method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990072291A (en) * 1998-02-12 1999-09-27 피터 토마스 Electronically programmable read-only memory and method for programming and reading the memory

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